[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #6 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Yesterday I updated the GPIO module and input/output work now.
https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/simple_gpio.py;h=aae041eb3e223bc34e74644072cad1c668270ed9;hb=08668544c65f4892867ce4bf73ed8b754c2409a3

Currently I'm looking at fitting in multiple GPIO configs in one WB data word.
This will be done by having a parametrisable for-loop to attach some of the
gpios to particular bytes of the WB data bus.

Also, now that I have a better understanding of layouts, I'll make a new layout
that encapsulates all parameters for one GPIO. Currently I have several signal
arrays that represent GPIO configs (n-bit array for oe, ie, o, i, etc.).

The new layout would keep all the gpio config under one umbrella so-to-speak,
and would allow me to do away with the current "csrbus" layout.

gpio_layout = (("oe", 1),
               ("ie", 1),
               ("puen", 1),
               ("pden", 1),
               ("o", 1),
               ("bank_sel", NUMBANKBITS),
               ("i", 1),
              )

This layout can then be created for each GPIO.
self.gpios = Array([Record(gpio_layout) for _ in range(n_gpio)])

The gpios configuration can then be generated using a for-loop and address (var
names temporary, will change to something more appropriate):
for cur_byte in range(WORDSIZE):
    gpios[bus.adr*WORDSIZE+cur_byte].eq(wb_data)

This wouldn't quite work as the gpio layout has an additional "i" signal, so
I'll probably have to keep this one separate. Will need some more thinking on
that.

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