[Libre-soc-bugs] [Bug 812] invalid access to 0x0 on startup leads to core hang

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=812

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to tpearson from comment #0)

> I am working on staggering the main rst pulse and the CPU reset pulse to fix
> this problem.

took a look: it's a mess, inside TestIssuer.  i added a state to the
Fetch FSM called "pre-idle" and it's not properly stopped.  there's
supposed to be a delay-count and it's running out too early.

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