[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #47 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Cesar Strauss from comment #41)
> I have split the new issue FSM out from the issue/execute FSM, and marked
> the places where the looping will be checked/done, and where PC/SRCSTEP will
> be updated.

This is old news by now, but, for the record, the Issue FSM now implements the
SRCSTEP VL loop, as well as the VL==0 vector skip loop.

Probably, the VL==0 loop could have been done in Fetch instead. Luke, do you
want me to do this, before moving to predication, or leave it for later?

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