[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Mar 18 14:26:46 GMT 2021


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so, just so you know, the final pseudo-code will be something like this:

       if not src_zeroing:
            while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
                print ("      skip", bin(1<<srcstep))
                srcstep += 1

       if not dest_zeroing:
            # same for dststep
            while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
                print ("      skip", bin(1<<dststep))
                dststep += 1

       if src_zeroing and ((1<<srcstep) & srcmask) == 0:
            RA = 0
            RB = 0
            RA = get_register_RA
            RB = get_register_RB

       result, Condition_Register = calc_operation(RA, RB)

       if dest_zeroing and ((1<<dststep) & srcmask) == 0):
            result = 0
            Condition_Register = EQzero

       if Rc=1: store_cr(Condition_Register)

so the first phase is to add src-step and dst-step "skipping", based
on which bits of the predicate mask(s) are zero

the second phase adds in src_zeroing / dest_zeroing which does NOT
skip the computation but instead feeds **ZEROs** into either the
input or the output

i leave it up to you whether you would prefer to implement the whole
FSM there, i will "catch up" adding zeroing unit tests.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list