[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Mar 17 13:29:41 GMT 2021


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar i've added a couple of extra ports so as to be able to read the
predicates.  INT will be easier, it can be done one-shot.  CR is
different, a little more complex.

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index aec56e44..2512d3ae 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -77,6 +77,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
         self.r_ports = {'ra': self.read_port("src1"),
                         'rb': self.read_port("src2"),
                         'rc': self.read_port("src3"),
+                        'pred': self.read_port("pred"), # for predicate mask
                         'dmi': self.read_port("dmi")} # needed for Debug (DMI)

@@ -129,6 +130,7 @@ class CRRegs(VirtualRegPort):
                         'cr_b': self.write_port("dest2")} # 4-bit,
         self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
                         'full_cr_dbg': self.full_rd2, # for DMI
+                        'cr_pred': self.read_port("cr_pred"), # for predicate
                         'cr_a': self.read_port("src1"),
                         'cr_b': self.read_port("src2"),
                         'cr_c': self.read_port("src3")}

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