[Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=604

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i'm going to try this:
@@ -189,7 +189,9 @@ class RADIX:
     def ld(self, address, width=8, swap=True, check_in_mem=False):
         print("RADIX: ld from addr 0x%x width %d" % (address, width))
-        shift = SelectableInt(0, 32)
+        (shift, mbits, pgbase) = self._decode_prte(addr)
+        #shift = SelectableInt(0, 32)
+

you can see at line 235 and 315 in mmu.vhdl that pts is assigned to shift
variable
https://github.com/antonblanchard/microwatt/blob/6523acc74344b95e7cceb83611fb8cb2a030c1a3/mmu.vhdl#L235

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