[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #45 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hi Cesar i took a look at the pc_i.ok this morning, yes you are right, things
will go awry with SVSTATE because we are currently not also setting SVSTATE
from the debug interface.

SVSTATE.srcstep (and dststep) are actual Sub-PC steppers so not resetting those
is quite serious.

for now what i suggest is to reset SVSTATE.srcstep and dststep to zero when
pc_i.ok is raised high (i will take care of this)

also as you suggested have pc_i.ok come on to the issue FSM and exit the loop.

later we can add SVSTATE to the DMI (and JTAG), then the rule will have to be
set, "please over DMI modify PC first then SVSTATE second".

also then have to get test_core.py to use the DMI interface to set SVSTATE
rather than put it into a SPR.

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