[Libre-soc-bugs] [Bug 656] New: add v3.0B BCD instructions to simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=656

            Bug ID: 656
           Summary: add v3.0B BCD instructions to simulator
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

3 new instructions are needed, for BCD:
* addg6s
* cdtbcd
* cbcdtd

these are on p109 book I section 3.3.9 v3.0C
https://ftp.libre-soc.org/PowerISA_public.v3.0C.pdf

to support cdtbcd and cbcdtd, two functions will need to be created:

*  BCD_TO_DPD
*  DPD_TO_BCD

these will need adding in src/openpower/decoder/helpers.py
and then added to the top of the code-generating template
in pywriter.py

to get the carry-out bit, the pseudocode for addg6s will need to be
rewritten into a "programmatic" way rather than a "here's the general
idea of how to get the 65th bit from a 64-bit add"

do i = 0 to 15
   dc[i] <- carry_out(RA[4*i:63] + RB[4*i:63])

will need to be changed to something like:

   temp <- (0b0 || RA) + (0b0 || RB)
   do i = 0 to 15
       dc[i] <- temp[4*i]

(something like that)

and unit tests will need writing which check that they're functional.

oh.  haha, they're already added, just not yet tested.
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/bcd.mdwn;hb=HEAD

entries will need to be added to minor_31.csv, based on this:
https://github.com/antonblanchard/microwatt/blob/f9654428ff28744dcf1ad4e7fe43604415689f36/decode1.vhdl#L206

OP_ADDG6S and OP_BCD will need to be added to power_enums.py:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_enums.py;hb=HEAD

also  addg6s cdtbcd cbcdtd to _insns in alphabetical order

TODO checklist *in this order* due to dependencies (edit as needed):

* add OP_* to power_enums.py    - TODO
* add insn asmcodes to _insns   - TODO
* add minor_31.csv entries      - TODO
* add DCT_TO_BCD helper         - TODO
* add BCD_TO_DCD helper         - TODO
* add cdtbcd unit test          - TODO
* add cbcdtd unit test          - TODO
* correct addg6s pseudocode     - TODO
* add addg6s unit test          - TODO

at each step, *other* unit tests (at least one) need to be run (doesn't
matter which ones) as a way to verify that no "damage" has been done,
no python syntax errors etc.

commits on each of the above to be done separately and pushed with
appropriate commit messages, matching each of the TODO checklist
bulletpoints.

progress (copy of each commit log message incl. hash) to be sent here.

-- 
You are receiving this mail because:
You are on the CC list for the bug.