[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
thank you Staf (and Jean-Paul), this is great, it unblocks the 4k SRAM
and the PLL can be done the same way.  the DFF-SRAM is slightly
different but could either be ignored for now or done differently.

unfortunately the critical reliance on NDA'd versions of FlexLib means
that i cannot give any kind of confirmation or perform iterative
development or debugging:

diff --git a/experiments12/Makefile b/experiments12/Makefile
index acd76db..5be0fc9 100755
--- a/experiments12/Makefile
+++ b/experiments12/Makefile
@@ -2,7 +2,7 @@

         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
+               DESIGN_KIT = FlexLib018

 #           YOSYS_FLATTEN = Yes
                      CHIP = chip

if removing that and reverting to sxlib:

        Python stack trace:
        #0 in                  <module>() at
/home/lkcl/soclayout/experiments12/coriolis2/settings.py:23
        #1 in          loadUserSettings() at
.../lib/python2.7/dist-packages/crlcore/helpers/__init__.py:441
        #2 in                  <module>() at
/home/lkcl/alliance-check-toolkit/bin/doChip.py:15
        Error was:
          No module named NDA.node180.tsmc_c018

settings.py contains this:


+from   NDA.node180.tsmc_c018 import techno, FlexLib, LibreSOCIO, LibreSOCMem

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