[Libre-soc-bugs] [Bug 579] c/c++ macros for inline assembly supporting svp64

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Jan 25 11:27:52 GMT 2021


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)

> we might want to split this into two parts, SV support for unmodified
> gcc/binutils, and SV support once enough has been added to gcc to support
> full length vectors as inline asm arguments.

good idea.  let's leave this one as SV support for unmodified gcc/binutils,
it's what we need right now, as quickly as possible.

> Also, what's the list of ops we actually need for this task to be considered
> complete?

it should be auto-generated from the python parsing code called "pagereader.py"
and the CSV file reading.  therefore the answer is "what we have in the
wiki: the CSV files and the pseudocode pages".

that list - the pseudocode - is what's been added to ISACaller - because it's
literally executed after translation to python - and the TestIssuer pipelines
were created afterwards.

example code on how to do this is here:

pagereader.py obtains the instruction-argument format (ISA class),
the new SVP64RM class obtains the SVP64 EXTRA2/3 information, you can
see how it's processed.

if you are attempting this by hand it is completely the wrong approach
that will create a huge maintenance burden in the future.

*do not* hand-create the macros: auto-generate them from python.

we do *NOT* want to have to update these macros by hand every single time a bug
is found or a new instruction added.

also please don't create bash scripts to do the same job, or duplicate the
code, or create rust code, or create c++ code to do the exact same job as
the existing pagereader.py

for now, then, because there is no FP pseudocode there are no FP operations
added.  this will have to be done later as a separate task.

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