[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #54 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #53)
> Congrats! Now, if you also apply something similar to that to int/fp
> registers, then you will have implemented basically what I proposed in bug
> #553.
> 
> One difference is int/fp registers (but not CR fields) go like (when
> counting in vector element order):
> r0, r32, r64, r96,
> r1, r33, r65, r97,
> r2, r34, r66, r98 -- wrapping around after 4 instead of 8 registers.
> 
> for r<N> the element-order index = ((N & 0b11111) << 2) | ((N & 0b1100000) >> 5)

This still works fine with microarchitectural lanes, all that happens is lanes
are instead:
lane 0: r0-r31   CR0-7   CR32-39
lane 1: r32-63   CR8-15  CR40-47
lane 2: r64-95   CR16-23 CR48-55
lane 3: r96-127  CR24-31 CR56-63

-- 
You are receiving this mail because:
You are on the CC list for the bug.