[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #41 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #40)
> (In reply to Luke Kenneth Casson Leighton from comment #39)
> 
> > it is important that there be a split there,
> 
> i think.   you'll have to check.

I have split the new issue FSM out from the issue/execute FSM, and marked the
places where the looping will be checked/done, and where PC/SRCSTEP will be
updated. test_issuer.py and test_issuer_svp64.py are still happy.

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