[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar here's where in ISACaller, after decoding (all done already by
PowerDecoder2, now), the srcstep is added on:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/caller.py;h=03bf16d2ed98d6746fb6bdbfca2a312db8c9e424;hb=HEAD#l892

you can see further down the write version.  then, even further down,
the "loop" which exits when SVSTATE.srcstep == VL-1

however the equivalent location - and i must apologise for this - is
handled by regspec_decode_read() and regspec_decode_write():

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_regspec_map.py;h=05ff4814e2504e3acbc5924b614031b460f8bd7c;hb=HEAD#l51

that's actually called here, get_byregfiles():
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;h=d3a66bb1e9916c50277b1d5b1dc2a859707fc90b;hb=HEAD#l493

which returns a dictionary of tuples *kine 516), which in turn gets used by
connect_read/write_ports(), which in turn calls connect_read/write_port()

that tuple is unpacked here:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;h=d3a66bb1e9916c50277b1d5b1dc2a859707fc90b;hb=HEAD#l388

(also at line 260 for connect_readport)

now, *at the moment* it's relatively straightforward: regspec_decode_read/write
could in theory be modified to return a Mux() based on is_vec being set.

     Mux(e.read1_isvec, e.svstate.srcstep + e.read1_data, e.read1_data)

something like that

for elwidth overrides that's going to be a *lot* more complex... but for
now, that Mux should "do the trick"

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