[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #0)

>     c) If any source or destination was a vector, keep issuing the
> instruction and increment SVSTATE.srcstep. Break when it reaches VL-1

or if the destination is a scalar.  but only after the instruction is executed.
 when predication is added this makes more sense because the loop stops at the
first nonzero source predicate bit.

>     d) set SVSTATE.srcstep to zero again

and only then allow PC to advance.

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