From bugzilla-daemon at libre-soc.org Sun Aug 1 05:18:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 04:18:54 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 --- Comment #21 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #20) > (In reply to dmitry.selyutin from comment #19) > > Pushed the changes into the master. Hopefully we can move to 657. Luke, > > should I mark it as resolved, or this should be done by you? > > once resolved we "lose" it in searches, and it makes tracking payments > very difficult. to help deal with that, we create user pages, > see http://libre-soc.org/lkcl for an example (to template), > and that helps when creating the RFPs (Requests for Payment) Actually, for the payment stuff, marking it as resolved with dmitry as the assignee and some money assigned to this bug will make it show up on the markdown generated by budget-sync (in /task_db/mdwn/ on the website) next time someone runs and uploads budget-sync's output. Example generated markdown (exact bugs out-of-date): ## Completed but not yet added to payees list * [Bug #145](https://bugs.libre-soc.org/show_bug.cgi?id=145): reference FP emulation using algebraic numbers -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 10:34:04 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 09:34:04 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 --- Comment #22 from Jacob Lifshay --- explanation of why addg6s is useful: https://libre-soc.org/irclog/%23libre-soc.2021-08-01.log.html#t2021-08-01T10:10:13 > addg6s is used for doing a BCD addition, like x86's daa instruction: > https://www.felixcloutier.com/x86/daa > afaict to do a bcd add of a and b, you do `add r, a, b` then > `addg6s t, a, b` then `add r, r, t` -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 12:04:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 11:04:10 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 --- Comment #23 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #21) > Actually, for the payment stuff, marking it as resolved with dmitry as the > assignee and some money assigned to this bug will make it show up on the > markdown generated by budget-sync (in /task_db/mdwn/ on the website) next > time someone runs and uploads budget-sync's output. this forces me, as the site administrator, to spend my time being the one to run that script and run the upload. this is not a reasonable expectation. additionally, the user page can be used by each team member to contain work-in-progress notes, where the sync program is completely devoid of any such information, containing (sterile) information solely and exclusively about payments. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 16:57:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 15:57:10 +0000 Subject: [Libre-soc-bugs] [Bug 653] investigate FFT, DCT, etc for REMAP in SVP64 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=653 --- Comment #21 from Luke Kenneth Casson Leighton --- LD-bitreverse does not work for iDCT due to needing to be bitreversed *and* half-swapped... those operations being applied in the *opposite* order from DCT. therefore LD-bitreverse needs to be downgraded to LD-shift and it is REMAP that needs the bitrev-halfswap and halfswap-bitrev modes. this makes LD-shift less of a priority -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 18:10:34 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 17:10:34 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 --- Comment #24 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #23) > (In reply to Jacob Lifshay from comment #21) > > > Actually, for the payment stuff, marking it as resolved with dmitry as the > > assignee and some money assigned to this bug will make it show up on the > > markdown generated by budget-sync (in /task_db/mdwn/ on the website) next > > time someone runs and uploads budget-sync's output. > > this forces me, as the site administrator, to spend my time being the one > to run that script and run the upload. > > this is not a reasonable expectation. True, hence why I think the script should be automatically run, say in a daily/hourly cron job. Normally this would be taken care of by CI (GitLab CI can be set to run on a time-based schedule), but we're still waiting on getting mailing lists set up: see bug #190 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 19:07:55 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 18:07:55 +0000 Subject: [Libre-soc-bugs] [Bug 663] New: implement SVP64 element-width overrides Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=663 Bug ID: 663 Summary: implement SVP64 element-width overrides Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- tasks: * convert all pseudocode: TODO bug #NNN * add elwidth support to ISACaller: TODO bug #NNN * implement simulator unit tests: TODO bug #NNN * implement in TestIssuer: TODO bug #NNN * implement SVP64 unit tests for TestIssuer: TODO bug #NNN -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 19:08:12 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 18:08:12 +0000 Subject: [Libre-soc-bugs] [Bug 663] implement SVP64 element-width overrides In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=663 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- URL| |https://libre-soc.org/openp | |ower/sv/implementation/ NLnet milestone|--- |NLNet.2019.10.Wishbone -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 19:09:56 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 18:09:56 +0000 Subject: [Libre-soc-bugs] [Bug 663] implement SVP64 element-width overrides In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=663 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=583 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 1 19:09:56 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 01 Aug 2021 18:09:56 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=663 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 2 22:20:07 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 02 Aug 2021 21:20:07 +0000 Subject: [Libre-soc-bugs] [Bug 653] investigate FFT, DCT, etc for REMAP in SVP64 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=653 --- Comment #22 from Luke Kenneth Casson Leighton --- LDST downgraded, REMAP upgraded to compensate. initial exploration almost complete, NTT will have to wait until GF ops are available. next is SVG autogeneration. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 5 11:50:21 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 05 Aug 2021 10:50:21 +0000 Subject: [Libre-soc-bugs] [Bug 665] New: very basic nmigen-to-c compiler needed Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 Bug ID: 665 Summary: very basic nmigen-to-c compiler needed Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- https://github.com/apertus-open-source-cinema/naps/blob/9ebbc0/naps/soc/cli.py#L17 for PowerDecoder and PowerDecoder2 the output is sufficiently complex that duplicating it (and maintaining a duplicate) is not sensible. therefore create a VERY basic nmigen-to-c converter through simple AST node tree-walking. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 09:42:32 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 08:42:32 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=583 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 09:42:32 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 08:42:32 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=665 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 18:17:58 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 17:17:58 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 Cesar Strauss changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |cestrauss at gmail.com --- Comment #1 from Cesar Strauss --- > for PowerDecoder and PowerDecoder2 the output is sufficiently > complex that duplicating it (and maintaining a duplicate) is not sensible. An alternative for this would be to convert to a C++ simulation using cxxrtl and wrap the evaluation function into a library. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 19:29:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 18:29:19 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 --- Comment #2 from Luke Kenneth Casson Leighton --- (In reply to Cesar Strauss from comment #1) > > for PowerDecoder and PowerDecoder2 the output is sufficiently > > complex that duplicating it (and maintaining a duplicate) is not sensible. > > An alternative for this would be to convert to a C++ simulation using cxxrtl > and wrap the evaluation function into a library. nice idea in theory however c++ and the associated template library it uses will not make it into the linux kernel. i took a look yesterday at _pyrtl.py, i did not realise it actually creates *python* code which is eval'd and compiled and then executed as a nameless function. this is extremely cool because the python code (which can be inspected by enabling a debug os.ENV var) is very basic and conversion to c should be extremely easy. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 20:34:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 19:34:16 +0000 Subject: [Libre-soc-bugs] [Bug 190] Setup Gitlab CI Runner for Kazan on a computer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=190 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Status|CONFIRMED |RESOLVED Resolution|--- |INVALID --- Comment #32 from Luke Kenneth Casson Leighton --- i've been thinking about this for some time, wondering what it is tgat nakes me reticentvto action it, and i don't feel comfortable hosting large amounts of automated output (and having to back it up, and pay for the hosting, and ask Alain to host a duplicate backup). instead please install a mailing list locally. mailman2 is trivial to set up. if there are important bugs found the report and repro conditions may be duplicated and an appropriate bugreport raised where *ONLY* the relevant and crucial information may be recorded for aufit purposes. even hosting "small" success reports is not useful information closing as invalid. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 20:35:22 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 19:35:22 +0000 Subject: [Libre-soc-bugs] [Bug 190] Setup Gitlab CI Runner for Kazan on a computer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=190 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|1 |0 Resolution|INVALID |--- Status|RESOLVED |UNCONFIRMED --- Comment #33 from Luke Kenneth Casson Leighton --- ah this is not the mailing list one. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 20:37:58 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 19:37:58 +0000 Subject: [Libre-soc-bugs] [Bug 190] Setup Gitlab CI Runner for Kazan on a computer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=190 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Assignee|addw at phcomp.co.uk |programmerjake at gmail.com -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 23:36:40 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 22:36:40 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #1 from Luke Kenneth Casson Leighton --- https://twitter.com/gatecatte/status/1163742441272487936 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 6 23:50:01 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 22:50:01 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #2 from Luke Kenneth Casson Leighton --- looks like archlinux extracted the symbiflow xc7a100t (etc) already, into an easy package: https://aur.archlinux.org/packages/symbiflow-arch-defs-nightly-bin-device-xc7a100t/ -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Aug 7 00:50:28 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 06 Aug 2021 23:50:28 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #3 from Luke Kenneth Casson Leighton --- https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series TARGET="arty_100" make -C counter_test fails: indicates "symbiflow_synth" command is missing, but there's no information online how to get - or build - that command (!) https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/toolchain_wrappers/symbiflow_synth -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Aug 7 17:32:31 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 07 Aug 2021 16:32:31 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #4 from Luke Kenneth Casson Leighton --- https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html#prerequisites -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 8 06:11:49 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 08 Aug 2021 05:11:49 +0000 Subject: [Libre-soc-bugs] [Bug 190] Setup Gitlab CI Runner for Kazan on a computer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=190 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 Status|UNCONFIRMED |CONFIRMED --- Comment #34 from Jacob Lifshay --- email is still required to notify those who pushed a commit that broke the tests. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 8 11:04:15 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 08 Aug 2021 10:04:15 +0000 Subject: [Libre-soc-bugs] [Bug 190] Setup Gitlab CI Runner for Kazan on a computer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=190 --- Comment #35 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #34) > email is still required to notify those who pushed a commit that broke the > tests. which can be set up locally on the machine, which is part of the VPN, and can use the local IP address of libre-soc.org 10.6.0.1 as an SMTP relay. installing ssmtpd would do the trick, it's extremely simple. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 8 15:49:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 08 Aug 2021 14:49:39 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #5 from Luke Kenneth Casson Leighton --- https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/environment.yml vtr, prjxray-tools, prjxray-db, symbiflow-yosys-plugins and yosys all were needed, opencd as well (debian package, there) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 9 19:36:40 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 09 Aug 2021 18:36:40 +0000 Subject: [Libre-soc-bugs] [Bug 660] "First developer steps" documentation page In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=660 dmitry.selyutin at 3mdeb.com changed: What |Removed |Added ---------------------------------------------------------------------------- Status|DEFERRED |IN_PROGRESS --- Comment #4 from dmitry.selyutin at 3mdeb.com --- Status: updated the docs with the intro into the world of markdown and pseudocode. That's quite a quick intro, since the document is already quite big; anyway, if you feel I forgot to tell something at this page, please, let me know. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 9 21:30:23 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 09 Aug 2021 20:30:23 +0000 Subject: [Libre-soc-bugs] [Bug 660] "First developer steps" documentation page In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=660 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of| |dmitry=250 payments (in EUR)| | for this task;| | TOML format| | --- Comment #5 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #4) > Status: updated the docs with the intro into the world of markdown and > pseudocode. looks great, dmitry. once you have this on an about homepage i'll close it as fixed. http://libre-soc.org/dmitry or perhaps http://libre-soc.org/3mdeb/dmitry use my page as a template http://libre-soc.org/lkcl -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 16:24:30 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 15:24:30 +0000 Subject: [Libre-soc-bugs] [Bug 660] "First developer steps" documentation page In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=660 --- Comment #6 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #5) > perhaps http://libre-soc.org/3mdeb/dmitry use my page as a template > http://libre-soc.org/lkcl created a stub for you. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 18:58:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 17:58:19 +0000 Subject: [Libre-soc-bugs] [Bug 653] investigate FFT, DCT, etc for REMAP in SVP64 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=653 --- Comment #23 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=413c083e4dd8452fae7c4e426851f1c19a7a9b8c DCT SVG image generator -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 19:19:25 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 18:19:25 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #1 from Luke Kenneth Casson Leighton --- Table 129:BCD-to-DPD translation 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 00_ 000 001 002 003 004 005 006 007 008 009 50_ 280 281 282 283 284 285 286 287 288 289 01_ 010 011 012 013 014 015 016 017 018 019 51_ 290 291 292 293 294 295 296 297 298 299 02_ 020 021 022 023 024 025 026 027 028 029 52_ 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 03_ 030 031 032 033 034 035 036 037 038 039 53_ 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 04_ 040 041 042 043 044 045 046 047 048 049 54_ 2C0 2C1 2C2 2C3 2C4 2C5 2C6 2C7 2C8 2C9 05_ 050 051 052 053 054 055 056 057 058 059 55_ 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 06_ 060 061 062 063 064 065 066 067 068 069 56_ 2E0 2E1 2E2 2E3 2E4 2E5 2E6 2E7 2E8 2E9 07_ 070 071 072 073 074 075 076 077 078 079 57_ 2F0 2F1 2F2 2F3 2F4 2F5 2F6 2F7 2F8 2F9 08_ 00A 00B 02A 02B 04A 04B 06A 06B 04E 04F 58_ 28A 28B 2AA 2AB 2CA 2CB 2EA 2EB 2CE 2CF 09_ 01A 01B 03A 03B 05A 05B 07A 07B 05E 05F 59_ 29A 29B 2BA 2BB 2DA 2DB 2FA 2FB 2DE 2DF 10_ 080 081 082 083 084 085 086 087 088 089 60_ 300 301 302 303 304 305 306 307 308 309 11_ 090 091 092 093 094 095 096 097 098 099 61_ 310 311 312 313 314 315 316 317 318 319 12_ 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 62_ 320 321 322 323 324 325 326 327 328 329 13_ 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 63_ 330 331 332 333 334 335 336 337 338 339 14_ 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 64_ 340 341 342 343 344 345 346 347 348 349 15_ 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 65_ 350 351 352 353 354 355 356 357 358 359 16_ 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 66_ 360 361 362 363 364 365 366 367 368 369 17_ 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 67_ 370 371 372 373 374 375 376 377 378 379 18_ 08A 08B 0AA 0AB 0CA 0CB 0EA 0EB 0CE 0CF 68_ 30A 30B 32A 32B 34A 34B 36A 36B 34E 34F 19_ 09A 09B 0BA 0BB 0DA 0DB 0FA 0FB 0DE 0DF 69_ 31A 31B 33A 33B 35A 35B 37A 37B 35E 35F 20_ 100 101 102 103 104 105 106 107 108 109 70_ 380 381 382 383 384 385 386 387 388 389 21_ 110 111 112 113 114 115 116 117 118 119 71_ 390 391 392 393 394 395 396 397 398 399 22_ 120 121 122 123 124 125 126 127 128 129 72_ 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3A9 23_ 130 131 132 133 134 135 136 137 138 139 73_ 3B0 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 3B9 24_ 140 141 142 143 144 145 146 147 148 149 74_ 3C0 3C1 3C2 3C3 3C4 3C5 3C6 3C7 3C8 3C9 25_ 150 151 152 153 154 155 156 157 158 159 75_ 3D0 3D1 3D2 3D3 3D4 3D5 3D6 3D7 3D8 3D9 26_ 160 161 162 163 164 165 166 167 168 169 76_ 3E0 3E1 3E2 3E3 3E4 3E5 3E6 3E7 3E8 3E9 27_ 170 171 172 173 174 175 176 177 178 179 77_ 3F0 3F1 3F2 3F3 3F4 3F5 3F6 3F7 3F8 3F9 28_ 10A 10B 12A 12B 14A 14B 16A 16B 14E 14F 78_ 38A 38B 3AA 3AB 3CA 3CB 3EA 3EB 3CE 3CF 29_ 11A 11B 13A 13B 15A 15B 17A 17B 15E 15F 79_ 39A 39B 3BA 3BB 3DA 3DB 3FA 3FB 3DE 3DF 30_ 180 181 182 183 184 185 186 187 188 189 80_ 00C 00D 10C 10D 20C 20D 30C 30D 02E 02F 31_ 190 191 192 193 194 195 196 197 198 199 81_ 01C 01D 11C 11D 21C 21D 31C 31D 03E 03F 32_ 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 82_ 02C 02D 12C 12D 22C 22D 32C 32D 12E 12F 33_ 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 83_ 03C 03D 13C 13D 23C 23D 33C 33D 13E 13F 34_ 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 84_ 04C 04D 14C 14D 24C 24D 34C 34D 22E 22F 35_ 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 85_ 05C 05D 15C 15D 25C 25D 35C 35D 23E 23F 36_ 1E0 1E1 1E2 1E3 1E4 1E5 1E6 1E7 1E8 1E9 86_ 06C 06D 16C 16D 26C 26D 36C 36D 32E 32F 37_ 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 1F8 1F9 87_ 07C 07D 17C 17D 27C 27D 37C 37D 33E 33F 38_ 18A 18B 1AA 1AB 1CA 1CB 1EA 1EB 1CE 1CF 88_ 00E 00F 10E 10F 20E 20F 30E 30F 06E 06F 39_ 19A 19B 1BA 1BB 1DA 1DB 1FA 1FB 1DE 1DF 89_ 01E 01F 11E 11F 21E 21F 31E 31F 07E 07F 40_ 200 201 202 203 204 205 206 207 208 209 90_ 08C 08D 18C 18D 28C 28D 38C 38D 0AE 0AF 41_ 210 211 212 213 214 215 216 217 218 219 91_ 09C 09D 19C 19D 29C 29D 39C 39D 0BE 0BF 42_ 220 221 222 223 224 225 226 227 228 229 92_ 0AC 0AD 1AC 1AD 2AC 2AD 3AC 3AD 1AE 1AF 43_ 230 231 232 233 234 235 236 237 238 239 93_ 0BC 0BD 1BC 1BD 2BC 2BD 3BC 3BD 1BE 1BF 44_ 240 241 242 243 244 245 246 247 248 249 94_ 0CC 0CD 1CC 1CD 2CC 2CD 3CC 3CD 2AE 2AF 45_ 250 251 252 253 254 255 256 257 258 259 95_ 0DC 0DD 1DC 1DD 2DC 2DD 3DC 3DD 2BE 2BF 46_ 260 261 262 263 264 265 266 267 268 269 96_ 0EC 0ED 1EC 1ED 2EC 2ED 3EC 3ED 3AE 3AF 47_ 270 271 272 273 274 275 276 277 278 279 97_ 0FC 0FD 1FC 1FD 2FC 2FD 3FC 3FD 3BE 3BF 48_ 20A 20B 22A 22B 24A 24B 26A 26B 24E 24F 98_ 08E 08F 18E 18F 28E 28F 38E 38F 0EE 0EF 49_ 21A 21B 23A 23B 25A 25B 27A 27B 25E 25F 99_ 09E 09F 19E 19F 29E 29F 39E 39F 0FE 0FF Table 130: DPD-to-BCD translation 0 1 2 3 4 5 6 7 8 9 A B C D E F 00_ 000 001 002 003 004 005 006 007 008 009 080 081 800 801 880 881 01_ 010 011 012 013 014 015 016 017 018 019 090 091 810 811 890 891 02_ 020 021 022 023 024 025 026 027 028 029 082 083 820 821 808 809 03_ 030 031 032 033 034 035 036 037 038 039 092 093 830 831 818 819 04_ 040 041 042 043 044 045 046 047 048 049 084 085 840 841 088 089 05_ 050 051 052 053 054 055 056 057 058 059 094 095 850 851 098 099 06_ 060 061 062 063 064 065 066 067 068 069 086 087 860 861 888 889 07_ 070 071 072 073 074 075 076 077 078 079 096 097 870 871 898 899 08_ 100 101 102 103 104 105 106 107 108 109 180 181 900 901 980 981 09_ 110 111 112 113 114 115 116 117 118 119 190 191 910 911 990 991 0A_ 120 121 122 123 124 125 126 127 128 129 182 183 920 921 908 909 0B_ 130 131 132 133 134 135 136 137 138 139 192 193 930 931 918 919 0C_ 140 141 142 143 144 145 146 147 148 149 184 185 940 941 188 189 0D_ 150 151 152 153 154 155 156 157 158 159 194 195 950 951 198 199 0E_ 160 161 162 163 164 165 166 167 168 169 186 187 960 961 988 989 0F_ 170 171 172 173 174 175 176 177 178 179 196 197 970 971 998 999 10_ 200 201 202 203 204 205 206 207 208 209 280 281 802 803 882 883 11_ 210 211 212 213 214 215 216 217 218 219 290 291 812 813 892 893 12_ 220 221 222 223 224 225 226 227 228 229 282 283 822 823 828 829 13_ 230 231 232 233 234 235 236 237 238 239 292 293 832 833 838 839 14_ 240 241 242 243 244 245 246 247 248 249 284 285 842 843 288 289 15_ 250 251 252 253 254 255 256 257 258 259 294 295 852 853 298 299 16_ 260 261 262 263 264 265 266 267 268 269 286 287 862 863 (888) (889) 17_ 270 271 272 273 274 275 276 277 278 279 296 297 872 873 (898) (899) 18_ 300 301 302 303 304 305 306 307 308 309 380 381 902 903 982 983 19_ 310 311 312 313 314 315 316 317 318 319 390 391 912 913 992 993 1A_ 320 321 322 323 324 325 326 327 328 329 382 383 922 923 928 929 1B_ 330 331 332 333 334 335 336 337 338 339 392 393 932 933 938 939 1C_ 340 341 342 343 344 345 346 347 348 349 384 385 942 943 388 389 1D_ 350 351 352 353 354 355 356 357 358 359 394 395 952 953 398 399 1E_ 360 361 362 363 364 365 366 367 368 369 386 387 962 963 (988) (989) 1F_ 370 371 372 373 374 375 376 377 378 379 396 397 972 973 (998) (999) 20_ 400 401 402 403 404 405 406 407 408 409 480 481 804 805 884 885 21_ 410 411 412 413 414 415 416 417 418 419 490 491 814 815 894 895 22_ 420 421 422 423 424 425 426 427 428 429 482 483 824 825 848 849 23_ 430 431 432 433 434 435 436 437 438 439 492 493 834 835 858 859 24_ 440 441 442 443 444 445 446 447 448 449 484 485 844 845 488 489 25_ 450 451 452 453 454 455 456 457 458 459 494 495 854 855 498 499 26_ 460 461 462 463 464 465 466 467 468 469 486 487 864 865 (888) (889) 27_ 470 471 472 473 474 475 476 477 478 479 496 497 874 875 (898) (899) 28_ 500 501 502 503 504 505 506 507 508 509 580 581 904 905 984 985 29_ 510 511 512 513 514 515 516 517 518 519 590 591 914 915 994 995 2A_ 520 521 522 523 524 525 526 527 528 529 582 583 924 925 948 949 2B_ 530 531 532 533 534 535 536 537 538 539 592 593 934 935 958 959 2C_ 540 541 542 543 544 545 546 547 548 549 584 585 944 945 588 589 2D_ 550 551 552 553 554 555 556 557 558 559 594 595 954 955 598 599 2E_ 560 561 562 563 564 565 566 567 568 569 586 587 964 965 (988) (989) 2F_ 570 571 572 573 574 575 576 577 578 579 596 597 974 975 (998) (999) 30_ 600 601 602 603 604 605 606 607 608 609 680 681 806 807 886 887 31_ 610 611 612 613 614 615 616 617 618 619 690 691 816 817 896 897 32_ 620 621 622 623 624 625 626 627 628 629 682 683 826 827 868 869 33_ 630 631 632 633 634 635 636 637 638 639 692 693 836 837 878 879 34_ 640 641 642 643 644 645 646 647 648 649 684 685 846 847 688 689 35_ 650 651 652 653 654 655 656 657 658 659 694 695 856 857 698 699 36_ 660 661 662 663 664 665 666 667 668 669 686 687 866 867 (888) (889) 37_ 670 671 672 673 674 675 676 677 678 679 696 697 876 877 (898) (899) 38_ 700 701 702 703 704 705 706 707 708 709 780 781 906 907 986 987 39_ 710 711 712 713 714 715 716 717 718 719 790 791 916 917 996 997 3A_ 720 721 722 723 724 725 726 727 728 729 782 783 926 927 968 969 3B_ 730 731 732 733 734 735 736 737 738 739 792 793 936 937 978 979 3C_ 740 741 742 743 744 745 746 747 748 749 784 785 946 947 788 789 3D_ 750 751 752 753 754 755 756 757 758 759 794 795 956 957 798 799 3E_ 760 761 762 763 764 765 766 767 768 769 786 787 966 967 (988) (989) 3F_ 770 771 772 773 774 775 776 777 778 779 796 797 976 977 (998) (999) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 19:24:48 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 18:24:48 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |programmerjake at gmail.com --- Comment #2 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #1) > Table 129:BCD-to-DPD translation sad case of wrapping ... maybe put on the wiki where you can use markdown tables? -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 20:57:59 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 19:57:59 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #3 from dmitry.selyutin at 3mdeb.com --- That's OK, I already use it. I'm planning to put it in the test (almost) exactly as is (except that there won't be two halves, they'll simply follow one after another), and do parsing there. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 21:02:27 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 20:02:27 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #4 from dmitry.selyutin at 3mdeb.com --- Actually I already have something which doesn't work. Need to re-check both the pseudocode and parsing. As an example, attempting to convert BCD 010 to DPD yields 0x008 instead of 0x010. Will investigate it. I'm somewhat concerned that 1000 iterations will take a lot of time, if we create a program for each iteration. Do we have some way to speed things up? -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 21:03:55 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 20:03:55 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #5 from dmitry.selyutin at 3mdeb.com --- (In reply to dmitry.selyutin from comment #4) > Do we have some way to speed things up? One of ideas which comes to mind is compiling a program which makes use of all 32 registers instead of checking the same register over and over again in a loop. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 21:23:05 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 20:23:05 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #6 from dmitry.selyutin at 3mdeb.com --- (In reply to dmitry.selyutin from comment #4) > As an example, attempting to convert BCD 010 to DPD yields 0x008 instead of 0x010. Will investigate it. Never mind, I'm stupid. These are not numbers in range 0..999, these are (what a surprise, huh?) binary coded decimals. So when they write 010... it actually means 0b000000010000 ((0x0 << 8) | (0x1 << 4) | (0x0 << 0)). -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 21:57:53 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 20:57:53 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #7 from dmitry.selyutin at 3mdeb.com --- OK, it looks like BCD => DPD works (still in progress, awfully slow). For now, I limited it with first 20 entries, and even this takes 42 seconds on my VM. For sure, we must invent the way to speed things up. I'm thinking of generating the assembly for all 32 registers; please, let me know, if you have better ideas (frankly I don't find my own idea attractive enough). -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 22:27:49 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 21:27:49 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- total budget (EUR)|200 |300 for completion of| | task and all| | subtasks| | budget (EUR) for|200 |300 this task,| | excluding| | subtasks' budget| | --- Comment #8 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #7) > OK, it looks like BCD => DPD works (still in progress, awfully slow). For > now, I limited it with first 20 entries, and even this takes 42 seconds on > my VM. For sure, we must invent the way to speed things up. yes, this has already been done, search "cases" i.e. "def case_" and you will find the technique used. happy to increase this by EUR 100 if you can adapt test_caller_bcd.py to use the technique. will post-edit this comment with the code for HDL running -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 10 22:28:50 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 10 Aug 2021 21:28:50 +0000 Subject: [Libre-soc-bugs] [Bug 242] OpenPOWER simulation unit tests are needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=242 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|6000 |5700 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 11 08:39:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 11 Aug 2021 07:39:19 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #9 from dmitry.selyutin at 3mdeb.com --- Updated the test with cdtbcd, written in the same fashion and spirit as cbcdtd ones. This one, of course, is slow as well. Luke, thank you for help on how to improve the performance, I'll update the test respectively. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 11 10:15:43 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 11 Aug 2021 09:15:43 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #10 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=889b2d55bb86177007d78cc2a9d232d0ff56cea6 not tested, i threw that together based on soc/simple/test_runner TestRunner class, you should easily get the idea from that. i created it because there's quite a lot in the HDL version that you have to ignore. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 13 08:57:36 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 13 Aug 2021 07:57:36 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 --- Comment #25 from Maciej Pijanowski --- Is this task considered finished? According to Dmitry it is (correct me if I'm wrong please). Luke, what is the procedure then to close the task? -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 13 12:09:07 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 13 Aug 2021 11:09:07 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 --- Comment #26 from Luke Kenneth Casson Leighton --- (In reply to Maciej Pijanowski from comment #25) > Is this task considered finished? > According to Dmitry it is (correct me if I'm wrong please). > > Luke, what is the procedure then to close the task? see comment #20, i have a mild preference for it to be closed when the unit tests confirm that it's correct. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 15 19:45:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 15 Aug 2021 18:45:19 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #11 from Jacob Lifshay --- GCC's DPD to binary (not BCD) conversion table: https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=libdecnumber/bid/bid2dpd_dpd2bid.h;hb=99dee82307f1e163e150c9c810452979994047ce#l145 binary (not BCD) to DPD conversion table: https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=libdecnumber/bid/bid2dpd_dpd2bid.h;hb=99dee82307f1e163e150c9c810452979994047ce#l4893 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 17 13:36:42 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 17 Aug 2021 12:36:42 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #1 from vklr at vkten.in --- Created attachment 134 --> https://bugs.libre-soc.org/attachment.cgi?id=134&action=edit multiple_function_units_write svg image SVG version of multiple_function_units_write. Please review. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 17 19:15:49 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 17 Aug 2021 18:15:49 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|0 |200 this task,| | excluding| | subtasks' budget| | total budget (EUR)|0 |200 for completion of| | task and all| | subtasks| | --- Comment #2 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #1) > Created attachment 134 [details] > multiple_function_units_write svg image > > SVG version of multiple_function_units_write. > Please review. ha, that looks really good, do drop it in place of the jpg in the wiki. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 17 19:16:44 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 17 Aug 2021 18:16:44 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|4400 |4200 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 17 20:57:59 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 17 Aug 2021 19:57:59 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #12 from Luke Kenneth Casson Leighton --- i tracked this down: https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl#L528 it's an implementation of addg6s in VHDL. the sum_with_carry variable is adding its two inputs, a and b, with an extra (65th) bit, just like we did in the pseudocode. what i would suggest is, simply creating a python function which does the equivalent of the pseudocode (and check it's the same as the microwatt version), and just make up some values to test. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 07:12:26 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 06:12:26 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #3 from vklr at vkten.in --- Created attachment 135 --> https://bugs.libre-soc.org/attachment.cgi?id=135&action=edit multiple_function_units_read svg image SVG Image of multiple_function_units_read In Second box(Long Add), wire to OR gate is blue; may be it has to be green? -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 11:38:24 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 10:38:24 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #4 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #3) > Created attachment 135 [details] > multiple_function_units_read svg image > > SVG Image of multiple_function_units_read > > In Second box(Long Add), wire to OR gate is blue; may be it has to be green? there are only 3 colours, purple for A green for B orange for X. those colours going in to a Function Unit have to match those going out. so yes, most likely you are correct. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 16:25:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 15:25:19 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #5 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #3) > Created attachment 135 [details] > multiple_function_units_read svg image > > SVG Image of multiple_function_units_read > > In Second box(Long Add), wire to OR gate is blue; may be it has to be green? i took a look: you see how "green" (B) goes in to Branch, Increment (1) and Increment (2)? that means that, into the OR gate, a corresponding "green" needs to go *out* of Branch, connected to the OR gate. at present there is only one green out of Increment (1) into the OR gate and another green out of Increment (2) into the same OR gate. the Red (X) likewise goes into all three... ah, and there is one too many blue :) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 16:27:55 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 15:27:55 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #6 from Luke Kenneth Casson Leighton --- Created attachment 136 --> https://bugs.libre-soc.org/attachment.cgi?id=136&action=edit screenshot of multi unit ok so here's a screenshot of the corrections needed, * branch is missing green and red from Branch to the OR gate * yes, Long Add, it should be green to the (2nd) OR gate there's a couple others, do check them. maybe review the write pending one as well, don't draw the lines *through* the Function Units! that's just for illustrative purposes. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 16:29:15 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 15:29:15 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #7 from vklr at vkten.in --- Uploaded and changed multiple_function_units.png with two SVG images; one for write and one for read. Also updated relevant page: https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:07:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:07:54 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #8 from vklr at vkten.in --- (In reply to Luke Kenneth Casson Leighton from comment #6) > Created attachment 136 [details] > screenshot of multi unit > > ok so here's a screenshot of the corrections needed, > > * branch is missing green and red from Branch to the OR gate > * yes, Long Add, it should be green to the (2nd) OR gate > > there's a couple others, do check them. maybe review the write pending > one as well, don't draw the lines *through* the Function Units! > that's just for illustrative purposes. Corrected and updated in git(website). Please review. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:09:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:09:16 +0000 Subject: [Libre-soc-bugs] [Bug 626] dev-env-setup script for verilator, ghdl, iverilog and cocotb In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=626 vklr at vkten.in changed: What |Removed |Added ---------------------------------------------------------------------------- total budget (EUR)|0 |250 for completion of| | task and all| | subtasks| | budget (EUR) for|0 |250 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:09:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:09:54 +0000 Subject: [Libre-soc-bugs] [Bug 634] sphinx - build, install and interface with projects In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=634 vklr at vkten.in changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|0 |150 this task,| | excluding| | subtasks' budget| | total budget (EUR)|0 |150 for completion of| | task and all| | subtasks| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:27:29 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:27:29 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- total budget (EUR)|200 |250 for completion of| | task and all| | subtasks| | budget (EUR) for|200 |250 this task,| | excluding| | subtasks' budget| | --- Comment #9 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #8) > (In reply to Luke Kenneth Casson Leighton from comment #6) > Corrected and updated in git(website). Please review. look really good. dependence cell one next. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:31:53 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:31:53 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Assignee|lkcl at lkcl.net |vklr at vkten.in total budget (EUR)|0 |300 for completion of| | task and all| | subtasks| | budget (EUR) for|0 |300 this task,| | excluding| | subtasks' budget| | NLnet milestone|--- |NLNet.2019.10.Wishbone parent task for| |384 budget allocation| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:32:18 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:32:18 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|4200 |3900 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:38:24 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:38:24 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- URL| |http://libre-soc.org/HDL_wo | |rkflow/symbiflow -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:42:23 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:42:23 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of| |lkcl=100 payments (in EUR)| |veera=300 for this task;| | TOML format| | budget (EUR) for|300 |400 this task,| | excluding| | subtasks' budget| | total budget (EUR)|300 |400 for completion of| | task and all| | subtasks| | --- Comment #6 from Luke Kenneth Casson Leighton --- veera, i am assuming you'd be happy with another EUR 300 :) this one is quite big, i did some research already so extra 100 for me. a wiki page is needed which at the minimum lists all the dependencies listed in environment.yaml and requirements.txt from comment #5. thisis quite important because NOWHERE online are these listed! then a devscript needed, i made some notes already, the notes to be removed and replaced with the actual script. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 17:59:44 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 16:59:44 +0000 Subject: [Libre-soc-bugs] [Bug 626] dev-env-setup script for verilator, ghdl, iverilog and cocotb In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=626 vklr at vkten.in changed: What |Removed |Added ---------------------------------------------------------------------------- NLnet milestone|--- |NLNet.2019.10.Wishbone -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:02:14 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:02:14 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #7 from Luke Kenneth Casson Leighton --- Created attachment 137 --> https://bugs.libre-soc.org/attachment.cgi?id=137&action=edit dpkg list in chroot of debian pacakges installed -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:04:14 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:04:14 +0000 Subject: [Libre-soc-bugs] [Bug 654] dev-env-setup script for symbiflow (arty A7-100T) In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=654 --- Comment #8 from Luke Kenneth Casson Leighton --- Created attachment 138 --> https://bugs.libre-soc.org/attachment.cgi?id=138&action=edit list of pip packages installed in schroot -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:08:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:08:46 +0000 Subject: [Libre-soc-bugs] [Bug 634] sphinx - build, install and interface with projects In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=634 vklr at vkten.in changed: What |Removed |Added ---------------------------------------------------------------------------- NLnet milestone|--- |NLNet.2019.10.Wishbone -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:09:52 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:09:52 +0000 Subject: [Libre-soc-bugs] [Bug 634] sphinx - build, install and interface with projects In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=634 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- parent task for| |384 budget allocation| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:10:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:10:10 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|3900 |3750 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:15:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:15:51 +0000 Subject: [Libre-soc-bugs] [Bug 626] dev-env-setup script for verilator, ghdl, iverilog and cocotb In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=626 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- parent task for| |384 budget allocation| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 18 18:16:03 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 18 Aug 2021 17:16:03 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|3750 |3500 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 16:53:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 15:53:39 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #13 from dmitry.selyutin at 3mdeb.com --- Hi Luke, I think I finally got it. Since the recent commits, we do the following: 1. Use VHDL algorithm as a reference implementation. 2. Instead of this fun with adders, we rely on big ints. 3. Instead of generating the product, we generate random BCDs. 4. And yes, we can batch it! -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 18:02:13 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 17:02:13 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #14 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #13) > Hi Luke, I think I finally got it. Since the recent commits, we do the > following: > 1. Use VHDL algorithm as a reference implementation. yes. full_adder64 (much as i like it) can be replaced with just (in python) "return a + b", and everywhere x[N] replaced with "(x>>N) & 0b1" or if in a test: "if x&(1< 2. Instead of this fun with adders, we rely on big ints. yes. but try to make it "obvious" and/or add comments. instead of: addg6s[lo + 3] = 0 addg6s[lo + 2] = 1 addg6s[lo + 1] = 1 addg6s[lo + 0] = 0 do addg6s |= 0b0110 << lo > 3. Instead of generating the product, we generate random BCDs. yyyeah, lots of them. _hopefully_ that will spam enough numbers at the pseudocode to give enough coverage, i.e. for the carry bit to be triggered with both 0 and 1 with an equal distribution. carry on two random numbers is a 50-50 probability, right? because it uses (ultimately) XOR? > 4. And yes, we can batch it! :) btw do keep to under an 80 char limit. two reasons: we cannot assume that all developers have massive hi-res screens (the recent new developers from India will not), and second, i use hi-res screens to get *more terminals* on-screen ==> more information, more depth of investigation, less work, less effort. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 18:43:28 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 17:43:28 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #15 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #14) First of all, your reply made me realize that I haven't pushed the changes. However, your replies led to some more changes, more below. :-) > yes. full_adder64 (much as i like it) can be replaced It's already replaced in trunk. > do > addg6s |= 0b0110 << lo This is not as close as it can be to `addg6s(lo + 3 downto lo) := "0110";`. The best option would be to assign parts of slice (I'm splitting the integer into bits). IIRC Python supports it, I will re-check. > > 3. Instead of generating the product, we generate random BCDs. > yyyeah, lots of them. Not that many. However, when I checked the code to see the number (16 * 31 currently, 1 register is not used), I found that somehow I swapped the loop. I've fixed it now, and pushed along with forgotten commits. > it uses (ultimately) XOR? I have no idea what Python uses, but most likely yes. I simply took the most obvious option to generate BCD in range 0..9. > btw do keep to under an 80 char limit. I'll re-check it. That said, I don't like how does DPD_TO_BCD_TABLE formatting look like after line-length change. It used to be much cleaner, and the only reason it's changed is the hard limitation. Any ideas on how to improve it are appreciated, I only thought about spaces. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 18:50:42 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 17:50:42 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #16 from dmitry.selyutin at 3mdeb.com --- (In reply to dmitry.selyutin from comment #15) > The best option would be to assign parts of slice (I'm splitting the integer > into bits). IIRC Python supports it, I will re-check. Done -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 18:56:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 17:56:16 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #17 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #15) > (In reply to Luke Kenneth Casson Leighton from comment #14) > > First of all, your reply made me realize that I haven't pushed the changes. doh, been there > However, your replies led to some more changes, more below. :-) > > > > yes. full_adder64 (much as i like it) can be replaced > > It's already replaced in trunk. fantastic. > > do > > addg6s |= 0b0110 << lo > > This is not as close as it can be to `addg6s(lo + 3 downto lo) := "0110";`. don't worry about it. > The best option would be to assign parts of slice (I'm splitting the integer > into bits). IIRC Python supports it, I will re-check. > it doesn't, which is why we created SelectableInt. > > > 3. Instead of generating the product, we generate random BCDs. > > yyyeah, lots of them. > > Not that many. However, when I checked the code to see the number (16 * 31 > currently, 1 register is not used), I found that somehow I swapped the loop. > I've fixed it now, and pushed along with forgotten commits. excellent > > it uses (ultimately) XOR? > > I have no idea what Python uses, but most likely yes. i meant in the abstract (back at gate level) > I simply took the most > obvious option to generate BCD in range 0..9. > > > btw do keep to under an 80 char limit. > > I'll re-check it. some GUI based editors have guide lines. another trick is "git diff" in an xterm 80x65 or so. if any line wraps, wark. > That said, I don't like how does DPD_TO_BCD_TABLE > formatting look like after line-length change. It used to be much cleaner, > and the only reason it's changed is the hard limitation. Any ideas on how to > improve it are appreciated, I only thought about spaces. yeah i did a global search replace vim ":%s/ / /g" and realised after it took away too much. reinserting one space inter-column would likely do it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 18:57:18 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 17:57:18 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #18 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #16) > (In reply to dmitry.selyutin from comment #15) > > The best option would be to assign parts of slice (I'm splitting the integer > > into bits). IIRC Python supports it, I will re-check. > > Done >>> x = 5 >>> x[2] Traceback (most recent call last): File "", line 1, in TypeError: 'int' object has no attribute '__getitem__' -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 19 18:59:42 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 17:59:42 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #19 from Luke Kenneth Casson Leighton --- if (a_in[hi] ^ b_in[hi] ^ (sum_with_carry[hi] == 0)): addg6s[lo:lo + 3 + 1] = [0, 1, 1, 0] niiice. ok so it looks pretty close to what was done in execute1.vhdl i like it. it's not terribly efficient, but really clear. good job. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 00:41:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 19 Aug 2021 23:41:51 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #10 from vklr at vkten.in --- Created attachment 139 --> https://bugs.libre-soc.org/attachment.cgi?id=139&action=edit svg image of dependence_cell_multi_pending.jpg SVG image of dependence_cell_multi_pending.jpg Please review. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 12:51:50 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 11:51:50 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- total budget (EUR)|250 |300 for completion of| | task and all| | subtasks| | budget (EUR) for|250 |300 this task,| | excluding| | subtasks' budget| | --- Comment #11 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #10) > Created attachment 139 [details] > svg image of dependence_cell_multi_pending.jpg > > SVG image of dependence_cell_multi_pending.jpg > > Please review. love the layout, it's very clear. two things which will significantly improve it (see these): https://ftp.libre-soc.org/dependence_cell_multi_pending.jpg https://ftp.libre-soc.org/dependence_cell_multi_pending.svg (1) there are places where the wires cross. because there are no colours, you can't work out which wires "join" and which "cross". could you put "dots" at the crossing points, like in the JPG? (2) once all the dots are there, could you colourise the wires that are all the same signal? (no need to do everything) i made a start on the colours but i messed some of them up, i don't know how. mainly the named inputs, and the named outputs, try to make them REALLY bright primary colours, lots of contrast. i leave it to you to decide the best ones? again, you don't need to do *everything* in colour, but at least everything that has an input name and an output name. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 14:17:17 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 13:17:17 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 --- Comment #20 from dmitry.selyutin at 3mdeb.com --- Let me know if we can mark this as completed so that I could update the status tracking. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 17:09:33 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 16:09:33 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #12 from vklr at vkten.in --- Created attachment 140 --> https://bugs.libre-soc.org/attachment.cgi?id=140&action=edit Updated colours and connections Updated colours and connections dots. Please review. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 18:09:49 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 17:09:49 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 vklr at vkten.in changed: What |Removed |Added ---------------------------------------------------------------------------- Attachment #140 is|0 |1 obsolete| | --- Comment #13 from vklr at vkten.in --- Created attachment 141 --> https://bugs.libre-soc.org/attachment.cgi?id=141&action=edit New correct file. New correct file as attachment. Somehow wrong file was uploaded: id 140. Updated colours and connection dots. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 19:31:35 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 18:31:35 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #14 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #13) > Created attachment 141 [details] > New correct file. > > New correct file as attachment. Somehow wrong file was uploaded: id 140. > > Updated colours and connection dots. brilliant, that looks really good. only thing, the yellow is so close to white, i can't quite make it out. if you can make it a slightly darker yellow, then please go ahead, replace the JPG on 6600scoreboard, and we can close this one as "DONE". nice work veera. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 19:33:58 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 18:33:58 +0000 Subject: [Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=657 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=656 --- Comment #21 from Luke Kenneth Casson Leighton --- yes (In reply to dmitry.selyutin from comment #20) > Let me know if we can mark this as completed so that I could update the > status tracking. yes perfect, this and the other one as well (the instructions themselves) bug #656. both can be closed as fixed. you've got them on the paaage.... https://libre-soc.org/3mdeb/ghostmansd/ yes, all good. RFP time - need to sort out with Maciej, about the percentage for you and percentage for 3mdeb. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 20 19:33:58 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 20 Aug 2021 18:33:58 +0000 Subject: [Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=656 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=657 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Aug 21 03:48:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 21 Aug 2021 02:48:51 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 --- Comment #15 from vklr at vkten.in --- Changed yellow with dark yellow colour for wire lines. Uploaded and changed dependence_cell_multi_pending.jpg with SVG image in git. Also updated relevant page: https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Aug 21 12:45:20 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 21 Aug 2021 11:45:20 +0000 Subject: [Libre-soc-bugs] [Bug 671] New: convert spec pseudocode to use XLEN width Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 Bug ID: 671 Summary: convert spec pseudocode to use XLEN width Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- all pseudocode needs to use XLEN width instead of hard-coded values 64 as width. due to MSB0 numbering GREAT CARE NEEDS TO BE TAKEN RS[56:63] becomes RS[XLEN-8:XLEN-1] things that operate on the entire number such as Logical XOR or "add" instructions DO NOT need conversion. Pseudo-code: RT <- (RA|0) + EXTS(SI) does NOT need conversion. prod[0:127] <- MULS((RA), EXTS(SI)) RT <- prod[64:127] needs conversion to: prod[0:XLEN*2] <- MULS(.....) RT <- prod[XLEN:XLEN*2-1] -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Aug 21 12:45:47 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 21 Aug 2021 11:45:47 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Blocks| |663 NLnet milestone|--- |NLNet.2019.10.Wishbone Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=663 [Bug 663] implement SVP64 element-width overrides -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Aug 21 12:49:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 21 Aug 2021 11:49:46 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #1 from Luke Kenneth Casson Leighton --- first priority, add an XLEN integer constant (not a SelectableInt) to the namespace in ISACaller. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 12:14:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 11:14:16 +0000 Subject: [Libre-soc-bugs] [Bug 672] New: create unit test "positional popcount" Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=672 Bug ID: 672 Summary: create unit test "positional popcount" Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- https://www.reddit.com/r/programming/comments/p0yn45/three_fundamental_flaws_of_simd/h9n30n9/?utm_source=reddit&utm_medium=web2x&context=3 https://github.com/clausecker/pospop/blob/master/safe.go -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 12:14:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 11:14:39 +0000 Subject: [Libre-soc-bugs] [Bug 659] SVP64 demo / unit test of CRM data-dependent ffirst mode implementing insertion sort In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=659 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=672 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 12:14:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 11:14:39 +0000 Subject: [Libre-soc-bugs] [Bug 672] create unit test "positional popcount" In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=672 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=659 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 12:15:01 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 11:15:01 +0000 Subject: [Libre-soc-bugs] [Bug 672] create SVunit test "positional popcount" In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=672 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Summary|create unit test |create SVunit test |"positional popcount" |"positional popcount" -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 12:15:15 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 11:15:15 +0000 Subject: [Libre-soc-bugs] [Bug 672] create SVP64 demo / unit test "positional popcount" In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=672 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Summary|create SVunit test |create SVP64 demo / unit |"positional popcount" |test "positional popcount" -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 14:14:53 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 13:14:53 +0000 Subject: [Libre-soc-bugs] [Bug 672] create SVP64 demo / unit test "positional popcount" In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=672 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- parent task for| |242 budget allocation| | NLnet milestone|--- |NLNet.2019.10.Wishbone -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 14:15:32 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 13:15:32 +0000 Subject: [Libre-soc-bugs] [Bug 659] SVP64 demo / unit test of CRM data-dependent ffirst mode implementing insertion sort In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=659 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|0 |242 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 15:40:15 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 14:40:15 +0000 Subject: [Libre-soc-bugs] [Bug 663] implement SVP64 element-width overrides In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=663 dmitry.selyutin at 3mdeb.com changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |dmitry.selyutin at 3mdeb.com Assignee|lkcl at lkcl.net |dmitry.selyutin at 3mdeb.com -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 15:40:29 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 14:40:29 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 dmitry.selyutin at 3mdeb.com changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |dmitry.selyutin at 3mdeb.com Assignee|lkcl at lkcl.net |dmitry.selyutin at 3mdeb.com -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 16:08:36 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 15:08:36 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #2 from Luke Kenneth Casson Leighton --- annoyingly i have discovered that the pseudocode parser, which is based on GardenSnake.py, does not do RS[EXPR:EXPR] only RS[NUM:NUM] this should be a relatively easy fix in parser.py i will investigate -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 16:15:12 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 15:15:12 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #3 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;h=4f11f6f14c996caf50ddb5a83e99c2a9e1e707c7;hb=refs/heads/master#l826 RS[0:XLEN-1] should match perfectly well there, needs investigating. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 17:00:44 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 16:00:44 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #4 from Luke Kenneth Casson Leighton --- works perfectly: RA[XLEN:XLEN - 1] fails with a syntax error: RA[XLEN:XLEN-1] because it's interpreted as a number - "-1" which matches against *two* tokens: {VARIABLE}{NUMBER} *not* {VARIABLE}{MINUSOPERATOR}{NUMBER} doh that's very annoying, and i'm not sure how to fix it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 18:06:30 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 17:06:30 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #5 from dmitry.selyutin at 3mdeb.com --- I managed to "teach" parser and and lexer XLEN, but I doubt this is how we want it to be handled. diff --git a/src/openpower/decoder/pseudo/lexer.py b/src/openpower/decoder/pseudo/lexer.py index aad11a0..ce79e6a 100644 --- a/src/openpower/decoder/pseudo/lexer.py +++ b/src/openpower/decoder/pseudo/lexer.py @@ -326,6 +326,7 @@ class PowerLexer: 'INDENT', 'DEDENT', 'ENDMARKER', + 'XLEN', ) # Build the lexer @@ -398,6 +399,11 @@ class PowerLexer: "default": "DEFAULT", } + def t_XLEN(self, t): + r'XLEN' + t.type = self.RESERVED.get(t.value, "XLEN") + return t + def t_NAME(self, t): r'[a-zA-Z_][a-zA-Z0-9_]*' t.type = self.RESERVED.get(t.value, "NAME") diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py index 4f11f6f..61376ab 100644 --- a/src/openpower/decoder/pseudo/parser.py +++ b/src/openpower/decoder/pseudo/parser.py @@ -721,6 +721,10 @@ class PowerParser: if name in regs + fregs: self.read_regs.add(name) + def p_XLEN(self, p): + """atom : XLEN""" + p[0] = ast.Constant(64) + def p_atom_name(self, p): """atom : NAME""" name = p[1] -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 18:25:53 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 17:25:53 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #6 from Luke Kenneth Casson Leighton --- too low level. already taken care of, see comment #1 what does need fixing is "XLEN-1" or in fact any expression "z-1" to be recognised as {EXPR} {MINUS} {NUMBER} and that's probably best done by stopping the lexer.py from recognising "minus" in t_NUMBER's regexp, and teaching the parser about a new BNF number "MINUS NUMBER" which returns t[2] after first inverting the Constant value in t[2] then have to worry about the ordering, because if the parser encounters that before it encounters extpressions we end up with exactly the same issue, sigh: {MINUS} followed by {NUMBER} gets eaten and replaced by ast.{-Constant} is exactly what we want to avoid, give {EXPR} {MINUS} {NUMBER} higher priority. i *think* that's achieved by getting the order right that BNF functions are added into parser.py. i think. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 18:31:14 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 17:31:14 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #7 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #4) > doh that's very annoying, and i'm not sure how to fix it. I'm by no means an expert in PLY, but we have the following there: r"""[-]?(\d+(\.\d*)?|\.\d+)([eE][-+]? \d+)?""" The sign is considered to be a part of the token. If I drop [-]?, it gets parsed. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 18:44:04 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 17:44:04 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #8 from dmitry.selyutin at 3mdeb.com --- (In reply to dmitry.selyutin from comment #7) > The sign is considered to be a part of the token. If I drop [-]?, it gets > parsed. RA[XLEN-XLEN:XLEN-1] = RB[XLEN-XLEN:XLEN-1] is converted to eq(RA[XLEN - XLEN:XLEN - 1 + 1], RB[XLEN - XLEN:XLEN - 1 + 1]) Also, I've checked that we indeed don't need XLEN to be known, it's a simple t_NAME. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 19:04:22 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 18:04:22 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #9 from Luke Kenneth Casson Leighton --- that's two bits of good news, can you re-run pyfnwriter and a full pywriter then lots of test_caller_*.py (all of them) before committing? once you commit that after tests pass i will run the soc test_issuer ones, and the ffmpeg media ones, to make sure all the existing pseudocode works and hasn't been damaged. amazed that was so simple. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 19:24:58 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 18:24:58 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #10 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #9) > that's two bits of good news, can you re-run pyfnwriter and a full pywriter > then lots of test_caller_*.py (all of them) before committing? Sure, I'll do it! Anyway, if it runs successfully, I think we _will_ break non-trivial cases like `(a - -b)` (I don't think these are handled in parser now). I think those are not used now, but anyway. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 19:34:13 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 18:34:13 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #11 from dmitry.selyutin at 3mdeb.com --- (In reply to dmitry.selyutin from comment #10) > I think we _will_ break non-trivial cases like `(a - -b)` (I don't think these are handled in parser now). Yes, we do break them, and even simpler ones, like simple negative numbers. Anyway, I still think this should be done at parser level. I'm checking it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 19:52:55 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 18:52:55 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #12 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #11) > (In reply to dmitry.selyutin from comment #10) > > I think we _will_ break non-trivial cases like `(a - -b)` (I don't think these are handled in parser now). > > Yes, we do break them, and even simpler ones, like simple negative numbers. yyep this is what i expected, can be fixed with a BNF case in parser.py comment #6 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 19:57:42 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 18:57:42 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |programmerjake at gmail.com --- Comment #13 from Jacob Lifshay --- usually unary minus is handled as a separate operator... See JavaScript's syntax as an example: https://262.ecma-international.org/#sec-unary-operators I can help out with this bug tomorrow, busy today. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 20:40:25 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 19:40:25 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #14 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #13) > usually unary minus is handled as a separate operator... > > See JavaScript's syntax as an example: > https://262.ecma-international.org/#sec-unary-operators > > I can help out with this bug tomorrow, busy today. ohh, a separate item in the BNF? so, atom would be: expr | number | negnumber | ... or.. oh wait, no i got it. like: unary = ~x | !x etc, you would also have: -x in that list. ok yeah, then that would also work for "EXPR - - NUMBER" it also i think solves the case of not matching against EXPR NUMBER -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 20:43:05 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 19:43:05 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #15 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #14) > (In reply to Jacob Lifshay from comment #13) > > usually unary minus is handled as a separate operator... > unary = > ~x > | !x > > etc, you would also have: > > -x > > in that list. yes, exactly! -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 20:54:36 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 19:54:36 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #16 from dmitry.selyutin at 3mdeb.com --- Actually the issue is simpler. We have `comparison MINUS`, which should've been `MINUS comparison`. I have no idea why it's called comparison, since it's more close to expr, but anyway. The only test that fails among $(find . -name "test_*caller*") is ./src/openpower/decoder/isa/test_caller_svstate.py. I don't see how this failure related to the changes, so I pushed them. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:05:29 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:05:29 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #17 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #15) > yes, exactly! okaaay, cool. rrright. well, ngggh the (very basic, initially-just-a-ply-example) parser was heavily simplified from the original BNF used by python 2 (which would have been what it was based on, back in... 2006). it therefore looks like unary ops are detected in the comparison BNF: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;h=4f11f6f14c996caf50ddb5a83e99c2a9e1e707c7;hb=HEAD#l638 i have nooo idea if adding "MINUS comparison" to that list would work or not. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:14:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:14:10 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #18 from Jacob Lifshay --- (In reply to dmitry.selyutin from comment #16) > Actually the issue is simpler. We have `comparison MINUS`, which should've > been `MINUS comparison`. I have no idea why it's called comparison, since > it's more close to expr, but anyway. The only test that fails among $(find . > -name "test_*caller*") is > ./src/openpower/decoder/isa/test_caller_svstate.py. I don't see how this > failure related to the changes, so I pushed them. I think the unary minus should be detected in the `unary` production, otherwise you have the issue that `-a < b` is parsed as `-(a < b)`, which is not desired. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:21:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:21:46 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #19 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #16) > ./src/openpower/decoder/isa/test_caller_svstate.py. I don't see how this > failure related to the changes, so I pushed them. ok i'll check out before that (commit 89622cf45a5b6c) and run it. it's probably a unit test that was already failing. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:55:32 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:55:32 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #20 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #19) > (In reply to dmitry.selyutin from comment #16) > > > ./src/openpower/decoder/isa/test_caller_svstate.py. I don't see how this > > failure related to the changes, so I pushed them. > > ok i'll check out before that (commit 89622cf45a5b6c) and run it. > it's probably a unit test that was already failing. yep, already failing. Not Your Problem :) mine to deal with. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:56:13 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:56:13 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of| |veera=300 payments (in EUR)| | for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:56:50 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:56:50 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|veera=300 |veera={amount=300, payments (in EUR)| |submitted=2021aug21} for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:57:22 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:57:22 +0000 Subject: [Libre-soc-bugs] [Bug 634] sphinx - build, install and interface with projects In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=634 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of| |veera={amount=150, payments (in EUR)| |submitted=2021aug21} for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Aug 22 21:57:45 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 22 Aug 2021 20:57:45 +0000 Subject: [Libre-soc-bugs] [Bug 626] dev-env-setup script for verilator, ghdl, iverilog and cocotb In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=626 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of| |veera={amount=250, payments (in EUR)| |submitted=2021aug21} for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 23 08:45:28 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 23 Aug 2021 07:45:28 +0000 Subject: [Libre-soc-bugs] [Bug 626] dev-env-setup script for verilator, ghdl, iverilog and cocotb In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=626 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|veera={amount=250, |veera={amount=250, payments (in EUR)|submitted=2021aug21} |submitted=2021-08-21} for this task;| | TOML format| | --- Comment #22 from Jacob Lifshay --- luke: toml local dates have to be of the form 2021-01-23, you can't use 2021jan23. https://toml.io/en/v1.0.0#local-date toml follows https://tools.ietf.org/html/rfc3339 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 23 08:46:35 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 23 Aug 2021 07:46:35 +0000 Subject: [Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=651 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|veera={amount=300, |veera={amount=300, payments (in EUR)|submitted=2021aug21} |submitted=2021-08-21} for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 23 08:47:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 23 Aug 2021 07:47:02 +0000 Subject: [Libre-soc-bugs] [Bug 634] sphinx - build, install and interface with projects In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=634 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|veera={amount=150, |veera={amount=150, payments (in EUR)|submitted=2021aug21} |submitted=2021-08-21} for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 23 09:30:38 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 23 Aug 2021 08:30:38 +0000 Subject: [Libre-soc-bugs] [Bug 626] dev-env-setup script for verilator, ghdl, iverilog and cocotb In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=626 --- Comment #23 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #22) > luke: toml local dates have to be of the form 2021-01-23, you can't use > 2021jan23. > https://toml.io/en/v1.0.0#local-date > toml follows https://tools.ietf.org/html/rfc3339 thx, i couldn't remember, was going to sort it out when the error occurred by running budgetsync -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 03:28:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 02:28:19 +0000 Subject: [Libre-soc-bugs] [Bug 673] New: Port power-instruction-analyzer to use new asm! macro instead of to-be-removed llvm_asm! macro Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=673 Bug ID: 673 Summary: Port power-instruction-analyzer to use new asm! macro instead of to-be-removed llvm_asm! macro Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: IN_PROGRESS Severity: enhancement Priority: High Component: Source Code Assignee: programmerjake at gmail.com Reporter: programmerjake at gmail.com CC: libre-soc-bugs at lists.libre-soc.org, programmerjake at gmail.com NLnet milestone: --- Rust's llvm_asm! macro was never intended to be stabilized, switch to using the new asm! macro that will be stabilized. new asm! macro RFC: https://github.com/rust-lang/rfcs/pull/2843 Currently blocked on asm! gaining support for clobbering xer and cr: https://github.com/rust-lang/rust/issues/88315 WIP branch: https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/tree/update-for-new-asm -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 13:18:24 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 12:18:24 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #21 from Luke Kenneth Casson Leighton --- https://libre-soc.org/irclog/%23libre-soc.2021-08-25.log.html#t2021-08-25T07:54:08 discussion about adding new "helper" routines. if this was not a specification that required a Formal Process for submitting (and voting on) by an independent Foundation (OPF) i would say "yes great idea" immediately to creating as many "helper" routines as we like and need. however as a *specification* the practice of creating references that need the reader to have read a second page (somewhere buried in a 1,300 page document) where they have no idea how to even find the information that they need, this makes the specification hostile to read. bottom line, it's not just "pseudocode", we cannot just think as programmers (only), we have to forward-think: 1) "how will this be received by the OpenPOWER Foundation ISA Working Group" 2) "how will users with near-zero-prior knowledge react to reading this" -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 16:13:04 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 15:13:04 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 dmitry.selyutin at 3mdeb.com changed: What |Removed |Added ---------------------------------------------------------------------------- Status|CONFIRMED |IN_PROGRESS --- Comment #22 from dmitry.selyutin at 3mdeb.com --- The progress so far is available in xlen branch. I've processed parts of fixedarith and fixedlogical; the latter needed some changes on the parser side (we haven't supported expressions in loops). I'm waiting for replies wrt test_pipe_caller_long.py, since it basically blocks me in testing mul instructions (and I suspect most of the rest). -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 17:17:31 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 16:17:31 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #23 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #22) > The progress so far is available in xlen branch. i hate branches, you know that, right? :) > I've processed parts of > fixedarith and fixedlogical; the latter needed some changes on the parser > side (we haven't supported expressions in loops). ah that makes sense. what you can show "works" just drop it into master branch. > I'm waiting for replies wrt test_pipe_caller_long.py, since it basically > blocks me in testing mul instructions (and I suspect most of the rest). jacob can help with that. jacob you need to adjust the dev-env-setup acript so that it can be run "straight" (and not part of an external non-libresoc redource) running test_issuer.py (from soc) is an important one, it compares against the HDL (which, obviously, has not changed) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 17:24:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 16:24:54 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #24 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #23) > jacob you need to adjust the dev-env-setup acript > so that it can be run "straight" (and not part of an external non-libresoc > redource) I already adjusted dev-env-setup https://git.libre-soc.org/?p=dev-env-setup.git;a=history;f=pia-install;h=5e8ee78d1087e7b9e6525d200468bb39f9854cd7;hb=6e6203c9017e0471070fcd1f606b37f87d723ac6 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 17:30:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 16:30:02 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #25 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #24) > > I already adjusted dev-env-setup > https://git.libre-soc.org/?p=dev-env-setup.git;a=history;f=pia-install; > h=5e8ee78d1087e7b9e6525d200468bb39f9854cd7; > hb=6e6203c9017e0471070fcd1f606b37f87d723ac6 fantastic, dmitry can you run that and check it -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 17:36:36 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 16:36:36 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #26 from Luke Kenneth Casson Leighton --- for i in 0 to 7 index <- (RS)[8*i:8*i+7] in bpermd, RS may be 32 16 or 8 bit. we need to decide what to do here. bpermd is one of those unusual ones, not so straightforward. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 17:42:08 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 16:42:08 +0000 Subject: [Libre-soc-bugs] [Bug 451] Add PowerPC64 to Rust's new inline assembly implementation In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=451 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|DrChat={amount=400, |DrChat={amount=400, payments (in EUR)|submitted=2021-05-17} |submitted=2021-05-17} for this task;| |programmerjake=0 TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 18:03:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 17:03:51 +0000 Subject: [Libre-soc-bugs] [Bug 672] create SVP64 demo / unit test "positional popcount" In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=672 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- NLnet milestone|NLNet.2019.10.Wishbone |NLNet.2019.10.Standards --- Comment #1 from Jacob Lifshay --- fix milestone to match parent task -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 18:12:43 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 17:12:43 +0000 Subject: [Libre-soc-bugs] [Bug 241] OpenPOWER SImulation is needed of standards In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=241 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|8750 |8600 this task,| | excluding| | subtasks' budget| | CC| |programmerjake at gmail.com --- Comment #16 from Jacob Lifshay --- forgot to account for budget assigned to #656 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 18:17:48 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 17:17:48 +0000 Subject: [Libre-soc-bugs] [Bug 389] Review all diagrams on wiki for translation into SVG In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=389 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- total budget (EUR)|150 |450 for completion of| | task and all| | subtasks| | --- Comment #8 from Jacob Lifshay --- forgot to account for budget assigned to #651 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 18:18:24 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 17:18:24 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|3500 |3200 this task,| | excluding| | subtasks' budget| | --- Comment #6 from Jacob Lifshay --- forgot to account for budget assigned to #651 through #389 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 18:50:24 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 17:50:24 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- Depends on| |674 See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=674 Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=674 [Bug 674] fix budget for #384 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Aug 25 23:48:41 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 25 Aug 2021 22:48:41 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC Power ISA Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 --- Comment #7 from Luke Kenneth Casson Leighton --- i always run nohup budget-sync then inspect the full output i need too review these because i haven't been fully tree balancing down the sub-bugs. needs a couple days not doing anything but budgets and RFPs. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 26 02:51:52 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 26 Aug 2021 01:51:52 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #27 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=a14ebcbc17e690976d054be5ec361c0ecc043c97 neat. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Aug 26 05:55:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 26 Aug 2021 04:55:46 +0000 Subject: [Libre-soc-bugs] [Bug 673] Port power-instruction-analyzer to use new asm! macro instead of to-be-removed llvm_asm! macro In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=673 --- Comment #1 from Jacob Lifshay --- Created a rustc pull request adding support for clobbering xer and cr: https://github.com/rust-lang/rust/pull/88350 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 14:36:53 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 13:36:53 +0000 Subject: [Libre-soc-bugs] [Bug 676] New: FORTRAN MAXLOC SVP64 example Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=676 Bug ID: 676 Summary: FORTRAN MAXLOC SVP64 example Product: Libre-SOC's first SoC Version: unspecified Hardware: Other OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Documentation Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- https://groups.google.com/g/comp.arch/c/5h6jzyESg5s create example SVP64 assembly for: int m2(int * const restrict a, int n) { int m, nm; int i; m = INT_MIN; nm = -1; for (i=0; i m) { m = a[i]; nm = i; } } return nm; } -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 14:37:45 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 13:37:45 +0000 Subject: [Libre-soc-bugs] [Bug 659] SVP64 demo / unit test of CRM data-dependent ffirst mode implementing insertion sort In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=659 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=676 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 14:37:45 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 13:37:45 +0000 Subject: [Libre-soc-bugs] [Bug 676] FORTRAN MAXLOC SVP64 example In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=676 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=659 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 14:38:52 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 13:38:52 +0000 Subject: [Libre-soc-bugs] [Bug 659] SVP64 demo / unit test of CRM data-dependent ffirst mode implementing insertion sort In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=659 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|242 |0 this task,| | excluding| | subtasks' budget| | NLnet milestone|--- |NLNet.2019.10.Wishbone parent task for| |242 budget allocation| | Blocks| |242 Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=242 [Bug 242] OpenPOWER simulation unit tests are needed -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 14:39:28 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 13:39:28 +0000 Subject: [Libre-soc-bugs] [Bug 676] FORTRAN MAXLOC SVP64 example In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=676 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- parent task for| |242 budget allocation| | NLnet milestone|--- |NLNet.2019.10.Wishbone -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 14:58:05 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 13:58:05 +0000 Subject: [Libre-soc-bugs] [Bug 676] FORTRAN MAXLOC SVP64 example In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=676 --- Comment #1 from Luke Kenneth Casson Leighton --- part 1: In Horizontal-First Mode this would use data-dependent fail-first Mode, which would test and truncate VL at the point where a[i] was less than m, creating a CR Vector in the process (sv.cmp.) part 2: SVP64 Branch new CTR Mode would skip over all elements that failed, decrementing CTR in the process. part 3: a second data-dependent ffirst would test and truncate VL where a[i] was GREATER-EQUAL than m part 4: a second branch CTR mode would likewise loop and decrement CTR -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Aug 27 22:42:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 27 Aug 2021 21:42:10 +0000 Subject: [Libre-soc-bugs] [Bug 676] FORTRAN MAXLOC SVP64 example In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=676 --- Comment #2 from Luke Kenneth Casson Leighton --- int m2(int * const restrict a, int n) { int m, nm; int i; m = INT_MIN; nm = -1; i=0; while (i m) { m = a[i]; nm = i; } i++; } return nm; } -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 09:21:23 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 08:21:23 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #28 from dmitry.selyutin at 3mdeb.com --- Updated the branch with some of div instructions. The "pipe" tests are fragile and there are 900+ tests failed even on master (perhaps this means that I did something wrong upon establishing pia and soc dependencies). Any help is appreciated. I'll continue updating the instructions; once I get to testing, I'll resolve issues, if any, cumulatively, then I'll rebase the branch atop of master. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 09:22:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 08:22:51 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #29 from dmitry.selyutin at 3mdeb.com --- (In reply to dmitry.selyutin from comment #28) > once I get to testing For now, I only check that pywriter can generate the Python code. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 09:26:55 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 08:26:55 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #30 from dmitry.selyutin at 3mdeb.com --- Also, a question on prtyd instruction. In specs we have the following: "s ⊕ (RS)i%8+7". In fixedlogical.mdwn, we have "s ^ (RS)[i*8+7]". Is it correct? -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 12:03:20 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 11:03:20 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #31 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #30) > Also, a question on prtyd instruction. In specs we have the following: "s ⊕ > (RS)i%8+7". In fixedlogical.mdwn, we have "s ^ (RS)[i*8+7]". Is it correct? look at section 1.3.2 the symbol is defined there. we obviously had to use the standard ASCII symbol for XOR. however you are probably referring to the use of "%" not "*" which looks like a bug in the v3.0B specification. it may have already been raised. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 12:11:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 11:11:16 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #32 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #28) > Updated the branch with some of div instructions. The "pipe" tests are > fragile and there are 900+ tests failed even on master (perhaps this means > that I did something wrong upon establishing pia and soc dependencies). Any > help is appreciated. jacob can you please help Dmitry by running the tests and investigating the software library that you are responsible for, it is holding Dmitry up. > I'll continue updating the instructions; once I get to testing, I'll resolve > issues, if any, cumulatively, then I'll rebase the branch atop of master. thid is precisely why i do not like branches. it would be much much better for the work to be done only in master branch by running individual tests and on confirmation of one instruction being functional to push it, then move on to the next one. even trying to do that, now, due to the large number of commits in a branch, is going to be a massive headache. divergence of branches is a huge operational inconvenience. we now have to do an all-or-nothing approach and it is being held up by jacob. jacob csn you please pay attention. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 12:17:08 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 11:17:08 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #33 from Luke Kenneth Casson Leighton --- https://libre-soc.org/irclog/%23libre-soc.2021-08-30.log.html#t2021-08-30T09:29:38 changing the element width to 32/16/8 on fields that are only 4 bit in width in the first place makes no sense. so anything that goes into CR leave it alone. we'll have to deal with that separately (in a different way), but element-width overrides will not be done on CRs. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 12:50:52 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 11:50:52 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #34 from Luke Kenneth Casson Leighton --- a new test in power_pseudo.py [0]*16] produces this: Module(body=[Expr(value=Call(func=Name(id='concat', ctx=Load()), args=[Constant(value=0)], keywords=[keyword(arg='repeat', value=Constant(value=16))]))]) astor dump Module( body=[ Expr( value=Call(func=Name(id='concat'), args=[Constant(value=0)], keywords=[keyword(arg='repeat', value=Constant(value=16))]))]) to source concat(0, repeat=16) where the following: [0]*(XLEN-16) instead produces this: Module(body=[BinOp(left=List(elts=[Constant(value=0)], ctx=Load()), op=Mult(), right=BinOp(left=Name(id='XLEN', ctx=Load()), op=Sub(), right=Constant(value=16)))]) astor dump Module( body=[ BinOp(left=List(elts=[Constant(value=0)]), op=Mult, right=BinOp(left=Name(id='XLEN'), op=Sub, right=Constant(value=16)))]) to source ([0] * (XLEN - 16)) this is a bug. the source code generated should have been: concat(0, repeat=XLEN-16) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 12:54:29 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 11:54:29 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #35 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;h=03d0fd5e6aca7128ecfa2d42d36be84e0ca0d353;hb=b3061c38ef984418e266c6f74b366a7e953840a5#l179 identify selectable int multiply pattern is not able to recognise [0] * (expression) only a Constant. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 13:16:27 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 12:16:27 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #36 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #35) > https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/ > decoder/pseudo/parser.py;h=03d0fd5e6aca7128ecfa2d42d36be84e0ca0d353; > hb=b3061c38ef984418e266c6f74b366a7e953840a5#l179 > > identify selectable int multiply pattern is not able to recognise > > [0] * (expression) > > only a Constant. sorted. commit 73d15d3c4c5550ef85fbd1ea68b9afca2500d0bd Author: Luke Kenneth Casson Leighton Date: Mon Aug 30 13:05:59 2021 +0100 also add pattern-recognition for just [0] * XLEN have to keep a close eye on this commit 39a0dc7397c592b4b53631b2284d142fd20ac485 Author: Luke Kenneth Casson Leighton Date: Mon Aug 30 13:03:53 2021 +0100 fix pattern-match for an expression such as "XLEN-16" when looking for concat substitutions [item] * NUMBER was replaced with concat(item, repeat=NUMBER) but [item] * (XLEN-16) was not matching by adding a HACK which spots ast.Binop then [item]*(XLEN-16) can be recognised -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 13:22:07 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 12:22:07 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=678 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 13:22:36 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 12:22:36 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #37 from Luke Kenneth Casson Leighton --- reviewing this one: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=6bc1419dbcd0ee84cd28c8867eaf7dae7954c4e5 - n <- 32 - do while n < 64 + n <- (XLEN/2) + do while n < XLEN if (RS)[n] = 1 then leave n <- n + 1 - RA <- n - 32 + RA <- n - (XLEN/2) 258 Pseudo-code: 259 260 n <- (XLEN/2) 261 do while n < XLEN 262 if (RS)[n] = 1 then 263 leave 264 n <- n + 1 265 RA <- n - (XLEN/2) 266 i *think* that's ok. the concept of a "word" is effectively redefined to "half-of-the-XLEN-width" which is something that's being done for FP "single" numbers. (any operation fmuls for example we are DEFINING as "actually the "s" means "do the FP op at half of the elwidth"") it does however get very weird for 8-bit. plus, we need to actually add *full* width cntlzd noted in bug #678 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 13:49:11 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 12:49:11 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #38 from Luke Kenneth Casson Leighton --- in the new RANGE helper, the inverted direction was missing - if start.value > end.value: # start greater than end, must go -ve - # auto-subtract-one (sigh) due to python range - end = ast.BinOp(p[6], ast.Add(), ast.Constant(-1)) - arange = [start, end, ast.Constant(-1)] this needed to be converted to: return range(start, end, -1) the inverted countdown (-1) was missing -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:02:11 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:02:11 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #39 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #31) > (In reply to dmitry.selyutin from comment #30) > > Also, a question on prtyd instruction. In specs we have the following: "s ⊕ > > (RS)i%8+7". In fixedlogical.mdwn, we have "s ^ (RS)[i*8+7]". Is it correct? > > look at section 1.3.2 the symbol is defined there. > we obviously had to use the standard ASCII symbol > for XOR. > > however you are probably referring to the use of > "%" not "*" which looks like a bug in the v3.0B > specification. > > it may have already been raised. yes it was http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2020-May/000046.html the spec is wrong. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:09:31 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:09:31 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #40 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=ff49e2ca41d621532795f960c715d7b7e9c5379c 332 * popcntw RA, RS 333 334 Pseudo-code: 335 336 do i = 0 to ((XLEN/32)-1) 337 n <- 0 338 do j = 0 to 31 339 if (RS)[(i*32)+j] = 1 then 340 n <- n+1 341 RA[(i*32):(i*32)+31] <- n this one doesn't look right. my intuition is that it should be redefined to be "counting halves of the input". more like: 336 do i = 0 to 1 337 n <- 0 338 do j = 0 to (XLEN/2)-1 339 if (RS)[(i*(XLEN/2))+j] = 1 then down at elwidth=8 it gets particularly hairy / interesting because the counting (both of the src RS into RA) would go into nibbles. but, actually, i think even that would work. not cherry-picking this one over. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:12:06 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:12:06 +0000 Subject: [Libre-soc-bugs] [Bug 679] New: not cherry-picking popcntw XLEN Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 Bug ID: 679 Summary: not cherry-picking popcntw XLEN Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=ff49e2ca41d621532795f960c715d7b7e9c5379c https://bugs.libre-soc.org/show_bug.cgi?id=671#c40 the subdivision i think needs to be on the inner loop not the outer loop -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:19:56 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:19:56 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #41 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=ef0109fb8e9d6e9f941cfa90bff389d522927c8e looks good. extsw. weird, but good. redefines the concept behind extsw as "sign-extend half of the elwidth" rather than sign-extend from a fixed hard-coded quantity of 32" -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:24:00 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:24:00 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #42 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=a9670992d6c9348d7f5c6d3d657a942a0b811f8e - RA <- EXTZ64(n) + RA <- EXTZ(n) aaahno. it would be better to over-ride the behaviour of EXTZ64 or at least not make that kind of "functional" change, right now. not cherry-picking this one. adding to bug #679 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:24:34 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:24:34 +0000 Subject: [Libre-soc-bugs] [Bug 679] not cherry-picking popcntw XLEN In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 --- Comment #1 from Luke Kenneth Casson Leighton --- not cherry-picking this one either, https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=a9670992d6c9348d7f5c6d3d657a942a0b811f8e https://bugs.libre-soc.org/show_bug.cgi?id=671#c42 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:24:49 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:24:49 +0000 Subject: [Libre-soc-bugs] [Bug 679] not cherry-picking popcntw XLEN In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Assignee|lkcl at lkcl.net |dmitry.selyutin at 3mdeb.com -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 14:25:48 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 13:25:48 +0000 Subject: [Libre-soc-bugs] [Bug 679] not cherry-picking popcntw XLEN or cnttz XLEN In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Summary|not cherry-picking popcntw |not cherry-picking popcntw |XLEN |XLEN or cnttz XLEN -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 16:07:42 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 15:07:42 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #43 from Luke Kenneth Casson Leighton --- moving on to fixedarith (the mul cases) found that auto-creation (auto-assignment) was stopping on expressions: prod[0:XLEN-1] <- something the variable "prod" does not exist so has to be auto-created however the detection was ONLY capable of recognising prod[0:31] <- something fixed: quite a big intrusive change so re-running test_issuer.py (for the 5th time today) https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=69c1f44388226d1fde2e6aa70ce2fd5bc660bd87 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 17:26:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 16:26:02 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #44 from Luke Kenneth Casson Leighton --- just going through cherry-picking from xlen branch (bleh) spotted that mulli doesn't have a short test, so made one https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=5e7b5ce86ded1f7686e4fa45538df0f0d7a5c5c2 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 17:35:03 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 16:35:03 +0000 Subject: [Libre-soc-bugs] [Bug 681] New: unit tests in ISACaller needed for madd* Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=681 Bug ID: 681 Summary: unit tests in ISACaller needed for madd* Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- there are no unit tests for madd* (because the pseudocode was only added as an afterthought, and the HDL hasn't been written) this makes it challenging to check the XLEN pseudocode changes. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 17:35:47 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 16:35:47 +0000 Subject: [Libre-soc-bugs] [Bug 681] unit tests in ISACaller needed for madd* In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=681 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Assignee|lkcl at lkcl.net |dmitry.selyutin at 3mdeb.com -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 17:37:08 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 16:37:08 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #45 from Luke Kenneth Casson Leighton --- created bug #681 there are no madd* unit tests in ISACaller (stand-alone for openpower-isa) so i have cherry-picked the madd* xlen branch code over for now, untested. this is fine because it can't do any "damage", with no actual implementation. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 20:08:25 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 19:08:25 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #46 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #40) > this one doesn't look right. my intuition is that it should be > redefined to be "counting halves of the input". The confusion is raised by these words from the spec: A count of the number of one bits in each word of regis- ter RS is placed into the corresponding word of register RA. This number ranges from 0 to 32, inclusive. I assumed "word" implies 32-bit. However, I think your rationale fits better. Let me re-check these. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 20:16:09 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 19:16:09 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #47 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #39) > (In reply to Luke Kenneth Casson Leighton from comment #31) > > (In reply to dmitry.selyutin from comment #30) > > however you are probably referring to the use of > > "%" not "*" which looks like a bug in the v3.0B > > specification. > > > > it may have already been raised. > > the spec is wrong. Yep, % is the thing I meant. The issue is still present at revision C. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 20:17:41 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 19:17:41 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #48 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #46) > The confusion is raised by these words from the spec: > > A count of the number of one bits in each word of regis- > ter RS is placed into the corresponding word of register > RA. This number ranges from 0 to 32, inclusive. > > I assumed "word" implies 32-bit. However, I think your rationale fits > better. Let me re-check these. with elwidth overrides we are wandering into a partiticularly important strategic part of SVP64, which is *not* approved yet by the OPF ISA WG and will need to be submitted via an official process. what we are doing - right now - is actually *defining* how SVP64 shall fit on top of these Power ISA scalar v3 0B operations. i.e. it is *not* up to the creators of the Power ISA v3.0B to say how the combination of Draft SVP64 shall behave: that is down to us. thus it is a slightly weird situation in which we have to think, "64 bit versions of these instructions, must be v3.0B compliant without a shadow of doubt, but 32 16 and 8 bit versions, those are our responsibility to think through and define... ... oh and then submit to the OPF ISA WG when they are ready" consequently, the actual wording of the v3.0B scalar spec is *not* helpful for defining what shall happen at 32, 16, or 8 bit: it is only strictly helpful at the full 64 bit -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 20:27:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 19:27:46 +0000 Subject: [Libre-soc-bugs] [Bug 679] not cherry-picking popcntw XLEN or cnttz XLEN In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 --- Comment #2 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #0) > https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff; > h=ff49e2ca41d621532795f960c715d7b7e9c5379c > > https://bugs.libre-soc.org/show_bug.cgi?id=671#c40 > > the subdivision i think needs to be on the inner loop > not the outer loop Yes, this is a typo. I think my eyes already dazzled at that point. I'll update it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 20:40:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 19:40:39 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #49 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #40) > but, actually, i think even that would work. This seems to do the trick: do i = 0 to 1 n <- 0 do j = 0 to ((XLEN/2)-1) if (RS)[(i*(XLEN/2))+j] = 1 then n <- n+1 RA[(i*(XLEN/2)):(i*(XLEN/2))+((XLEN/2)-1)] <- n -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Aug 30 22:54:40 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 21:54:40 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #50 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #49) > (In reply to Luke Kenneth Casson Leighton from comment #40) > > but, actually, i think even that would work. > > This seems to do the trick: > > do i = 0 to 1 > n <- 0 > do j = 0 to ((XLEN/2)-1) > if (RS)[(i*(XLEN/2))+j] = 1 then > n <- n+1 > RA[(i*(XLEN/2)):(i*(XLEN/2))+((XLEN/2)-1)] <- n > > ...the last line looks particularly impressive. much joy. let's write a spec that wins an obfuscation contest, double bonus points. much as i am tempted by that possibility, can i suggest, a temp var or two: e = XLEN/2-1 do i = 0 to 1 s = i*XLEN/2 n <- 0 do j = 0 to e if (RS)[s+j] = 1 then n <- n+1 RA[s:s+e] <- n or other mercifully short temp var names -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 00:53:59 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 30 Aug 2021 23:53:59 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #51 from Luke Kenneth Casson Leighton --- - EA <- b + EXTS(D) - RT <- [0]*56 || MEM(EA, 1) + EA <- b + EXTSREG(D) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) nope, sorry dmitry, i said we musn't add new helper functions, unless there is an absolute critical need that there is absolutely no other way. in this case EXTS already does the job due to already having been designed to do "dynamic" bitlength (setting bits to 256). -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 01:33:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 00:33:39 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #52 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fc68ee12c54f7f096a2631a9254db30fe4cde4e8 again, this one, it's important not to do changes to use an undocumented arbitrary helper function the idea here us, this pseudocode ACTUALLY will be submitted as ACTUAL v3.N specification with an OFFICIAL Request For Change to the OpenPOWER ISA. therefore all and any "helper" routines have to have a full audit, review, full justification, documentation, explanation, and finally submission to the ISA WG. i.e. a total pain in the ass. if we can simply overload EXTS64 via operator-overloading then when the pseudocode is submitted *without* EXTSREG the *reviewer* says, "this is meaningless please change it" *now* we have justification. in addition i said we are not doing width chsnges yet: width is currently hardcoded to 64. the *second* phase once hardcoded numbers *ONLY* have been replaced by XLEN will be to look at functions and try XLEN=32/16/8 one incremental step at a time, one task at a time. the larger the task the more critically important it is to ONLY strictly do that one regular task. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 06:30:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 05:30:39 +0000 Subject: [Libre-soc-bugs] [Bug 652] First part of implementing the vector-math library for Kazan and rustc In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=652 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|programmerjake={amount=1000 |programmerjake={amount=1000 payments (in EUR)|,submitted=2021-06-18} |,paid=2021-06-23} for this task;| | TOML format| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 07:34:48 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 06:34:48 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #53 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #32) > (In reply to dmitry.selyutin from comment #28) > > Updated the branch with some of div instructions. The "pipe" tests are > > fragile and there are 900+ tests failed even on master (perhaps this means > > that I did something wrong upon establishing pia and soc dependencies). Any > > help is appreciated. > > jacob can you please help Dmitry by running the tests and investigating > the software library that you are responsible for, it is holding Dmitry > up. I tried: https://libre-soc.org/irclog/%23libre-soc.2021-08-31.log.html#t2021-08-31T05:48:58 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 08:06:21 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 07:06:21 +0000 Subject: [Libre-soc-bugs] [Bug 679] not cherry-picking popcntw XLEN or cnttz XLEN In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 --- Comment #3 from dmitry.selyutin at 3mdeb.com --- popcntw -- pushed -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 11:47:09 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 10:47:09 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=458 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 11:47:09 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 10:47:09 +0000 Subject: [Libre-soc-bugs] [Bug 458] PartitionedSignal needs nmigen constructs "m.If", Switch etc In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=458 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=671 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 11:47:38 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 10:47:38 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=594 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 11:47:38 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 10:47:38 +0000 Subject: [Libre-soc-bugs] [Bug 594] create nmigen RFC for Dynamic Partitioned signals support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=594 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=671 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 12:22:14 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 11:22:14 +0000 Subject: [Libre-soc-bugs] [Bug 679] not cherry-picking popcntw XLEN or cnttz XLEN In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=679 --- Comment #4 from Luke Kenneth Casson Leighton --- (In reply to dmitry.selyutin from comment #3) > popcntw -- pushed > > https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff; > h=ab7c88d9a686f341c5af9ffd5b68175e0b67bb55 got it, looks good. updated to include shortened tempvars https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=cc990388b1f29c87f4d7ff53edbef9d34312b6f8 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 12:25:08 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 11:25:08 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #54 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #53) > I tried: > https://libre-soc.org/irclog/%23libre-soc.2021-08-31.log.html#t2021-08-31T05: > 48:58 brilliant, thanks jacob. ghostmansd: fixedload.mdwn reviewed and cherry-picked over. am finding that although it's tedious as hell the xlen branch is working because the cherry-picking forces me to read each individual patch (and run unit tests to confirm it). if you can let me do the cherry-picking, that will make me do the testing. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 13:06:21 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 12:06:21 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #55 from Luke Kenneth Casson Leighton --- all the div/mod patches are cherry-picked as well, unit tests pass. 4 hours ago Dmitry Selyutin fixedarith: switch modsd to XLEN 4 hours ago Dmitry Selyutin fixedarith: switch divdeX to XLEN 4 hours ago Dmitry Selyutin fixedarith: switch divdX to XLEN 4 hours ago Dmitry Selyutin fixedarith: switch modsw to XLEN 4 hours ago Dmitry Selyutin fixedarith: switch divweuX to XLEN 4 hours ago Dmitry Selyutin fixedarith: switch divweX to XLEN 4 hours ago Dmitry Selyutin fixedarith: switch divwX to XLEN -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 20:16:27 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 19:16:27 +0000 Subject: [Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=671 --- Comment #56 from dmitry.selyutin at 3mdeb.com --- (In reply to Luke Kenneth Casson Leighton from comment #54) > (In reply to Jacob Lifshay from comment #53) > if you can let me do the cherry-picking, that will make me do the > testing. I think it's what we have to do for now, but I actually dislike it. Ideally I should be able to test everything out-of-box. Since tests from soc look like way too beefy for machine I possess, I think we should eventually make talos do the job. This, however, has its difficulties as well (pia, rust, pip, other potential problems which I'm not aware about yet). -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 20:30:43 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 19:30:43 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 --- Comment #3 from Luke Kenneth Casson Leighton --- ok so the idea here is to have the bare minimum code-generator which is actually executable c code. it is reasonable to assume (for now) that the maximum Signal width will be 64-bit, but not reasonable to assume it will stay that way. therefore, part of the project involves creating some macro-templates for Signal arithmetic (in c) and having the compiler spit out both the macros and their usage. nmigen: comb += x.eq(y + 5) c output (or close to it): #define SIGNAL uint64_t #define SADD(res, x, y) (res = x + y) .... SADD(x, y, 5) something like that. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 20:36:48 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 19:36:48 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 Jacob Lifshay changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |programmerjake at gmail.com --- Comment #4 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #3) > ok so the idea here is to have the bare minimum code-generator which is > actually executable c code. it is reasonable to assume (for now) that > the maximum Signal width will be 64-bit, but not reasonable to assume > it will stay that way. > > therefore, part of the project involves creating some macro-templates > for Signal arithmetic (in c) and having the compiler spit out both > the macros and their usage. I'd expect that it'll work better for the C to be completely de-generic-ified, and not use a mountain of undecipherable macros to make everything work, being able to read the generated code would be nice :) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 21:01:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 20:01:19 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 --- Comment #5 from Luke Kenneth Casson Leighton --- (In reply to Jacob Lifshay from comment #4) > I'd expect that it'll work better for the C to be completely > de-generic-ified, and not use a mountain of undecipherable macros to make > everything work, being able to read the generated code would be nice :) signals unfortunately are not limited in length in any way, shape or form. there is no such concept in c as a basic integer type capable of adding 4,096 bits. consequently, macros (or macros hiding functions) are unavoidable. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 21:02:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 20:02:02 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 --- Comment #6 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #5) > signals unfortunately are not limited in length in any way, shape or form. > there is no such concept in c as a basic integer type capable of adding > 4,096 bits. (cxxsim uses c++ templates. compile-times are off the charts as a result) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Aug 31 21:48:22 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 31 Aug 2021 20:48:22 +0000 Subject: [Libre-soc-bugs] [Bug 665] very basic nmigen-to-c compiler needed In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=665 --- Comment #7 from Jacob Lifshay --- (In reply to Luke Kenneth Casson Leighton from comment #5) > (In reply to Jacob Lifshay from comment #4) > > > I'd expect that it'll work better for the C to be completely > > de-generic-ified, and not use a mountain of undecipherable macros to make > > everything work, being able to read the generated code would be nice :) > > signals unfortunately are not limited in length in any way, shape or form. > there is no such concept in c as a basic integer type capable of adding > 4,096 bits. > > consequently, macros (or macros hiding functions) are unavoidable. there's an easy solution: use arrays when signals are more than 64-bits: typedef uint32_t signal_word_t; typedef uint64_t signal_dword_t; #define SIGNAL_WORD_BITS 32 #define SIGNAL_ARRAY_SIZE(bits) \ (((size_t)(bits) + (SIGNAL_WORD_BITS - 1)) / SIGNAL_WORD_BITS) static inline size_t saturating_sub(size_t a, size_t b) { return a >= b ? a - b : 0; } static inline void add_signal( signal_word_t *restrict out, const signal_word_t *in0, const signal_word_t *in1, size_t bits) { size_t i; signal_dword_t carry = 0; for(i = 0; bits > 0; i++) { signal_dword_t sum = (signal_dword_t)in0[i]; sum += (signal_dword_t)in1[i] + carry; carry = sum >> SIGNAL_WORD_BITS; if(bits < SIGNAL_WORD_BITS) sum &= (1ULL << bits) - 1; out[i] = (signal_word_t)sum; bits = saturating_sub(bits, SIGNAL_WORD_BITS); } } void cast_unsigned_signal( signal_word_t *restrict out, size_t out_bits, const signal_word_t *in, size_t in_bits) { size_t i; for(i = 0; out_bits > 0; i++) { signal_word_t v = in_bits > 0 ? in[i] : 0; // assumption: `in` is already padded with zero bits // to fill out the last word if(out_bits < SIGNAL_WORD_BITS) v &= (1ULL << out_bits) - 1; out[i] = v; out_bits = saturating_sub(out_bits, SIGNAL_WORD_BITS); in_bits = saturating_sub(in_bits, SIGNAL_WORD_BITS); } } void openpower_add(openpower_regs *regs) { // replace with actual code: signal_word_t ra[SIGNAL_ARRAY_SIZE(64)]; signal_word_t rb[SIGNAL_ARRAY_SIZE(64)]; signal_word_t rt[SIGNAL_ARRAY_SIZE(64)]; signal_word_t lhs[SIGNAL_ARRAY_SIZE(256)]; signal_word_t rhs[SIGNAL_ARRAY_SIZE(256)]; signal_word_t sum[SIGNAL_ARRAY_SIZE(256)]; ra[0] = (signal_word_t)regs.ra; ra[1] = regs.ra >> SIGNAL_WORD_BITS; rb[0] = (signal_word_t)regs.rb; rb[1] = regs.rb >> SIGNAL_WORD_BITS; cast_unsigned_signal(lhs, 256, ra, 64); cast_unsigned_signal(rhs, 256, rb, 64); add_signal(sum, lhs, rhs, 256); cast_unsigned_signal(rt, 64, sum, 256); regs.rt = ((signal_dword_t)rt[1] << SIGNAL_WORD_BITS) | rt[0]; } -- You are receiving this mail because: You are on the CC list for the bug.