[Libre-soc-bugs] [Bug 633] custom run of ulx3s with 85k LUTs 5G part, and 128 mbyte (1 gigabit) SDRAM

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=633

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ISPPAC-CLK5406D-01SN48I/2751347

nuts.  Lattice VERSA ECP5 has a block buffer/generator IC which creates
the PCIe master clock.

it'll be nowhere near as simple as "just wire out PCIe from the FPGA".

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