[Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=604

--- Comment #50 from Tobias Platen <libre-soc at platen-software.de> ---
I went back through the git revision history.

Those numbers had been wrong from the beginning, but at that time I did not
realize that those were wrong. It would be correct if pgbase were 64 bits.

commit 11753fd5bfa447d53ed3b8c81243d9063a20da4b
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Mar 9 12:38:08 2021 +0000

    move ISACaller RADIX MMU class to separate module

commit 91b3f9682737d5c9adf8a6bfcd2be15ad8bf4465
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Mar 9 12:30:02 2021 +0000

    add pgtable and pte calculation to RADIX ISACaller

def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
        """
        x"00" & r.pgbase(55 downto 19) &
        ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
        "000";
        """
        mask16 = genmask(mask_size+5, 16)
        zero8 = SelectableInt(0, 8)
        zero3 = SelectableInt(0, 3)
        res = selectconcat(zero8,
                           pgbase[8:45],              #
                           (prtbl[45:61] & ~mask16) | #
                           (addrsh       & mask16),   #
                           zero3
                           )
        return res

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