[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #86 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #83)

> >                  +----> CORE (aka test_issuer).

>   I may have been too fast in my reading. You want to use ls180
>   as the core. In that case, it is correct. Sorry.

yes, sorry, you have been focussing, i left it until you are out of
"big development mode".  ls180 is the name of the cell which contains
Litex peripherals, JTAG, and also test_issuer.

(btw latest commits on coriolis2, track completion ratio 100%!  w00t!
now i will try putting the full core back in, see what happens.
will have to expand the ioring to match)

-- 
You are receiving this mail because:
You are on the CC list for the bug.