[Libre-soc-bugs] [Bug 508] decide package size and pin allocation for 180nm ASIC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=508

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #4)
> We have to go with a Graetek one as these have existing wireframes.

blech, ok.

> Otherwise one need to pay tooling for getting your own wireframe and this a
> few $10K and not accounted for in the NLNet budget.
> Other packagers imec has access to typically don't want to be bothered with
> low volumes.

ok then the 14x20 body size, 0.5mm pitch QFP-128 lead-length 1.6mm, no
need for the EP.

is it best to do an io ring that roughly matches that?

N: 38
S: 38
E: 26
W: 26

or can we get away with 32-32-32-32?

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