[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #6 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> 1107 #                 r.wb.stb <= '0';
> 1108 #               -- We only ever do reads on wishbone
> 1109 #               r.wb.dat <= (others => '0');
> 1110 #               r.wb.sel <= "11111111";
> 
> missed the wb.sel.
> 
> just set comb += r.wb.sel.eq(-1)

It's inside of an 'if rst=1' block, you said to ignore all code inside such
blocks:

```
1100 #             if rst = '1' then
1101 # On reset, clear all valid bits to force misses
1102 #               for i in index_t loop
1103 #                   cache_valids(i) <= (others => '0');
1104 #               end loop;
1105 #                 r.state <= IDLE;
1106 #                 r.wb.cyc <= '0';
1107 #                 r.wb.stb <= '0';
1108 #               -- We only ever do reads on wishbone
1109 #               r.wb.dat <= (others => '0');
1110 #               r.wb.sel <= "11111111";
1111 #               r.wb.we  <= '0';
```

-- 
You are receiving this mail because:
You are on the CC list for the bug.