[Libre-soc-bugs] [Bug 475] cxxsim improvements

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=475

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #13)
> > it is quite normal to expect the remaining bits (MSBs) to be set to zero,
> > and also for any bits that will not fit in the LHS to be thrown away.
> > 
> > this for example is how all 1s are set: x.eq(~0) or x.eq(-1) where x is
> > unsigned and way less than 64 bit.
> 
> Any non-zero update triggers the issue, provided that the signal being
> updated has a width greater than 32 bits.

interesting.  that's a very important distinction that should go in the
nmigen bugreport.  i suspect it's likely down to the use of ctypes.

it would be worthwhile specifically adding in very long signal unit tests
(128, 256, 512 bit).

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