[Libre-soc-bugs] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=138

--- Comment #12 from Staf Verhaegen <staf at fibraservi.eu> ---
On 23/11 a meeting was organised to discuss raodmap for tape-out of this 180nm
prototype. Due delay in progress for both standard cell and Coriolis
development the tape-out date has been moved to 2/12. One month is foreseen for
verification so all input need to be available 30/10. Following milestones have
been put forward to get there:

- now: freeze first version of libre-soc code, without any macro blocks
  on-chip RAM syntehsized to flip-flops
- 2/10: First layout of scaled standard cells
- 16/10: First dry run of P&R and test of tape-out flow with Europractice.
- 30/10:
  - Final code freeze of libre-soc nmigen code.
  - Final standard cell library
  - SRAM block finished
  - IO cell tested and finalized
  - PLL available
- 2/12: Hard deadline for tape-out submission of final layout.

This that need to be done from libre-soc side:
- now: finalize IO definition for current design (Luke & Staf)
- 30/10:
  - Finalize peripherals + IO
  - Finish MMU design + cache (#450, ...)
  - Determine expected operating frequency + align with PLL spec
  - Determine SRAM block dimensions + implement it

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