[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #74 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #73)

>   If by the new routing algorithm, you mean the buffer insertion,

yes, what you added recently

>   in fact, it should slightly decrease the density (the inserted
>   buffer increase the area).

interesting.

>     As long as the routing complete, this kind of density is not
>   a problem.

ahh ok.

> It reflect the highly connected nature of the netlist
>   and the effectiveness of the routing.

well, we are still around 17 incomplete routes (out of 100,000+)
err no i'm out by an order of magnitude on that

     - Track Segment Completion Ratio ........................ 100%
[1020210+18]
     - Wire Length Completion Ratio ....................... 100%
[61786063+1360]
     - Wire Length Expand Ratio ........................... 4.07%
[min:59367975]
     - Unrouted horizontals ........................................ 88.89%
[16]
     - Unrouted verticals ........................................... 11.11%
[2]
     - Done in ............................................... 7m 4.86s,
846.8Mb

one *million* tracks!

-- 
You are receiving this mail because:
You are on the CC list for the bug.