[Libre-soc-bugs] [Bug 498] New: JTAG ECP5 "tap" needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=498

            Bug ID: 498
           Summary: JTAG ECP5 "tap" needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

https://raw.githubusercontent.com/Spritetm/hadbadge2019_fpgasoc/4ae8277c45e17e316bb4d46ce625c1507506cd36/soc/top_fpga.v
https://github.com/emard/ulx3s-misc/blob/27338b0081b3b441f2fa77769350fa777bd3bcf9/examples/jtag_slave/hdl/top/top_jtagg_slave.v
https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/4ae8277c45e17e316bb4d46ce625c1507506cd36/soc/top_fpga.v

examples of how to "tap" into the (undocumented) JTAGG port on an ECP5.
this is very similar to Xilinx BSCANE2

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