[Libre-soc-bugs] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=72

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
    parent task for|                            |191
  budget allocation|                            |
 total budget (EUR)|0                           |4000
  for completion of|                            |
       task and all|                            |
           subtasks|                            |

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