[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Sep 21 17:35:58 BST 2020


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
         Depends on|                            |493

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #3)

> For pure nmigen code maybe the JTAG simulation infrastructure could be ported
> from cocotb to pysim/cxxsim. But I guess due to the use of litex the

i have a *very* basic unit test now with DMI2JTAG operational and reading


staf looking at the VCD files it seems that the addresses are stored in
reverse-bit-order which is quite interesting but has no impact on functionality

i may add one more unit test (JTAG wishbone read/write) and then i am going
to add this to ls180.

staf it would be nice to have DMI2TAG added to c4m jtag tap.py

Referenced Bugs:

[Bug 493] DMI JTAG SERDES needed, to be translated from
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