[Libre-soc-bugs] [Bug 488] Build test serdes on 180nm test chip for oct2020

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=488

Staf Verhaegen <staf at fibraservi.eu> changed:

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                 CC|                            |staf at fibraservi.eu

--- Comment #3 from Staf Verhaegen <staf at fibraservi.eu> ---
Prof. Dimitri Galayko @ LIP6 is already working on a PLL for the tape-out
including a VCO.
I don't see how you guys could do an analog design for the October tape-out as
you don't have access to the PDK. Also the paper is just a simulation excercise
which has not been verified in silicon.
I would also think there is enough to do on the digital side for the Power core
+ GPU extension for the October tape-out.

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