[Libre-soc-bugs] [Bug 519] Get output from ulx3s serial port to show up in minicom

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Oct 18 01:19:46 BST 2020


--- Comment #1 from Cole Poirier <colepoirier at gmail.com> ---
Hi Luke, having some difficulty. There is no longer a cpu_variant standardjtag,
it has become standardjtaggpiotest. You have instructed me to not make the
below change (versa_ecp5.py), but to make the bottom-most change that makes
standardjtag into standardjtaggpiotest (sim.py). This seems like a
contradiction to me, but I may be misunderstanding your instructions. How would
you like me to resolve this?

diff --git a/src/soc/litex/florent/versa_ecp5.py
index 8774b849..a001476e 100755
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -69,7 +69,7 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC):
             cpu_cls      = LibreSoC,
-            cpu_variant  = "standardjtag",
+            cpu_variant  = "standardjtaggpiotest",

diff --git a/src/soc/litex/florent/libresoc/core.py
index 81bd0dfc..10ad9396 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -13,7 +13,7 @@ from libresoc.ls180 import io
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180",
+CPU_VARIANTS = ["standard", "standard32", "standardjtaggpiotest", "ls180",

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