[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 8 20:12:22 BST 2020


--- Comment #66 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #64)
> (In reply to Cole Poirier from comment #62)
> > Can I import it into icache.py 
> no.  said this twice now.

Yes, but I have a thick head :)

> > or
> > should I be writing the test in the same file as wb_get().
> yes.  said that twice now, too. 

I get nervous and panicky with this kind of stuff as you know, I'm continuing
to work on that.

> > How is wb_get
> > connected to ICache? Like this?
> > sim.add_sync_process(wrap(icache_test(icache)))
> > sim.add_sync_process(wrap(wb_get(icache, icache_mem, "ICACHE")))
> > ```
> yes.


> > > in other words look at icache.py unit test and instead of the SRAM add the
> > > wb_get as the sync process with a nicely pre-prepared mem dict (that
> > > contains 100 randomly created keys and values)
> > 
> > I don't see how the wb_get fn can be used in icache.py given the global
> > variable... though I think it's likely I'm showing my python ignorance here.
> that's why i said (third time) put the test in the same file.
> > Of course, I was just starting from the working dcache_mmu_test
> indeed.
> we don't yet know how to use mmu in icache mode, it will need some research,
> reading some of microwatt tests for example.

Ok will do... I'm not sure they have a test for that. I just looked through all
the icache* and mmu* files in microwatt and other than the test I've already
translated into icache.py from icache_tb.vhdl they are all C, assembly, or
binaries, I don't see an HDL test for MMU-ICache.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list