[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 2 12:27:30 BST 2020


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
jean-paul this is what i have created.  it is... "excessive" however
will illustrate the point, very well.  a "real" (28/14/7nm) SoC will
have *more* clock/voltage domains than this!

i will push this to pinmux and soclayout so you can run it yourself and
see what you think.

the results will be displayed by "make pinmux" before being put into

chip['chip.domains'] = {'GPIO': ['p_gpio_8',
 'JTAG': ['p_jtag_tms', 'p_jtag_tdi', 'p_jtag_tdo', 'p_jtag_tck'],
 'SD': ['p_sdcard_cmd',
 'SDR': ['p_sdram_dm_0',
 'TWI': ['p_i2c_sda', 'p_i2c_scl'],
 'UART': ['p_uart_tx', 'p_uart_rx']}


chip['chip.clocks'] = 
     {'MSPI': 'p_spi_master_clk',
      'SD': 'p_sdcard_clk',
      'SDR': 'p_sdram_clock',
      'TWI': 'p_i2c_scl'}

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