[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #101 from Staf Verhaegen <staf at fibraservi.eu> ---

> But, what we must be sure of, is the interface.

Still am not 100% sure what exactly you mean with interface here and want to
avoid any possible misinterpretation.

> If I divert from HFNS to chip/corona creation, what's inside the I/O pads
> is not important. From what you (Staf) said, that seems ok, but it would
> be better if you can confirm.

My IO cells will have pins that will be connected directly to pins of the
CORONA.
The bonding pad is included in the IO cell.

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