[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #98 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Jean-Paul.Chaput from comment #96)

>   I understand. To avoid putting extra specifications, the fact that
>   there is different clocks could be directly guessed from the I/O pad
>   netlist (at "chip" level). I think it is not very difficult to
>   create disjoined parts in the I/O pad ring.
>     The big question is, will each part be made of an assembly of pxlib
>   pads *or* will Staf add some other kind with different wiring
>   strategies? Before I upgrade the I/O pad "router" I would need a
>   clear understanding of the I/O pads physical interface.

I suppose in the end my IO library will need to be used or does pxlib handle
ESD protection and IO voltage level shifting ?
What different kind of wiring strategies are you thinking about ?

Also does this need urgent feedback as I would like to first finish the
standard cell layout.

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