[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #93 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #89)
> I had not noticed before writing comment 16 in bug 532, but the 16-bit
> immediate compressed encoding is very very similar, in function and
> possibilities, to the extend-next-insn opcode I'd suggested before.

what you propose sounds perfectly reasonable for single-issue designs of
10-20 years ago.

i really, really do not want this proposal to go down the route of
adding yet more complexity at the 16-bit level, re-expanding length
based on deep-dive multi-bit selections:

* first level EXTNNN selection analysis
* second level FSM selects 16-bit
* third level selects bit0=1,bit15=15 to indicate compressed.immediate mode
* FOURTH level BACK to 32-bit (or greater) based on multi-bit brownfield
  encoding patterns?

no.  this is too much.

the complexity is too great for high performance multi-issue designs
to withstand.

length-mode decoding really must be kept to the absolute bare minimum, with
no "bleed-back" between 1st pipeline stage decode and 2nd stage.

SV is already going to require a *THREE* stage instruction decode.

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