[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #60 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #59)

> Break it down even further into one table for each fpga wiring, and a shared
> table for wiring those colours to the STLINKv2?

if you review the cabling for the VERSAECP5 you'll find that that is exactly
what i have done.  do you see a separate STLINKV2 cable picture for the
VERSAECP5?

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