[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Nov 10 15:48:23 GMT 2020


https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #26)

> Correct, the clock signal for the libre-soc is an output of the PLL block.
> It's the task of Jean-Paul and Dimitri to align the layout of the PLL with
> the clock-tree synthesis in Coriolis.
> Dimitri has the standard cell library at hand and will place the cells
> himself in the PLL block, also for the bypass. The reference clock is an
> input to the PLL block coming from an IO cell.

brilliant.  i will create a dummy module that has the same API (comment #21)
which for test purposes wires Ref-in to PLL-out.

-- 
You are receiving this mail because:
You are on the CC list for the bug.


More information about the libre-soc-bugs mailing list