[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #53 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #50)
>
> utterly confusing. put explicitly "note the tab" and actually mark it using
> gimp with an arrow pointing to the tab.
> 
> also action instructions in comment #47.

Ok. So do that with the upside image that has the same orientation as the JTAG
pinout and get rid of the right-side-up image?

Working on the instructions in #47, didn't want to remove the instructions
until I have finished adding the checklist that will replace it.


(In reply to Luke Kenneth Casson Leighton from comment #52)
> (In reply to Luke Kenneth Casson Leighton from comment #51)
> > i'll add a similar arrow pointing on the fig10 tomorrow.
> 
> done here:
> https://libre-soc.org/HDL_workflow/2020-11-03_14-08.png
> 
> if you can gimp-edit the images to match it will stop people getting
> confused about which way up the connector is

Ah I see. So keep both STLINKV2 images, or only the one matching the
orientation of fig 10 but coloured?... actually that will require a new photo
won't it as the tab is not visible in the current photo of the STLINKV2 with
the same orientation as fig 10.

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