[Libre-soc-bugs] [Bug 393] Hook up L2 Cache to Wishbone/LDST Wrappers

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Jun 20 20:35:20 BST 2020


--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Yehowshua from comment #7)
> Aha. So l0_cache.py **isn't** RTL -

it is indeed the RTL.

> its just a mock of what the RTL would do.

no, it's a combination of different classes that includes a "test"
class (the current L0CacheBuffer) which, as the docstring says,
allows us to "move on" in other areas of the code without the
memory architecture being a major blocker

it also contains sub-components which are needed for the "production"

now, if we don't have time before the Oct 2020 deadline, L0CacheBuffer
*will* be the RTL that ends up being taped out.

this would be bad, because it can't handle misaligned ld/st and it
is deliberately hard-limited to one LD/ST at a time.

> So, would you want me to fit RTL into that?

see comment #1 and the link to the incremental strategy that i outlined.

i advocate that we go one step at a time - forget L1 Cache entirely for now
as it is a distraction.

if we can get a TestMemoryLoadStoreUnit written - *no cache nothing
its sole purpose being to write to TestMemory* which can then be
connected into L0CacheBuffer, then dropping in either BareLoadStoreUnit
*or* CacheLoadStoreUnit *OR* the cache code that you would like to write
is an absolutely trivial one-line change.

however without everything complying with that LoadStoreInterface, none
of that is possible.

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