[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Jun 20 19:43:56 BST 2020


--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
moving to this bugreport

(In reply to Yehowshua from https://bugs.libre-soc.org/show_bug.cgi?id=382#c15)
> > which would only copy over a subset of wen signals.  and on certain
> > granularities would overrun the wen array.
> Oh yeah. I implicitly in my mind recognized you need to modify that for 64
> bits.

yes.  it melted my brain a bit that granularity is specified in number of
bits, not number of subdivisions.

and that nmigen Memory likewise has this convention.

we can't go 128 bit wide with this code without modifying it because
it directly ties SRAM width to Wishbone width.

and Wishbone is not permitted to be 128 bit (which is a pain, for us).

we could however do odd-even at bit 3 of the address, and have *pairs*
of 64 bit Wishbone-accessible SRAMs.

but, for an internal SRAM (for boot purposes and test purposes) i don't
think we need that level of high performance access (128 bit wide data)

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