[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #35)

> Use PowerISA? 

i'm happy with that.

> PowerPC seems overly specific to old versions of the ISA,
> though that *is* what gcc, llvm, and rust uses (powerpc64). Maybe PPC64?

sounds like it excludes 32bit.


> > 
> >         self.dive_abs_overflow_32 = Signal(reset_less=True)
> >         self.dive_abs_overflow_64 = Signal(reset_less=True)
> 
> see DivOutputStage for the rest of the overflow calculation:
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/div/output_stage.py;
> h=88a9ec1eec4bbc4ebb3fece42bbe235a13ae57ff;hb=HEAD#l65
> 
> > 
> > ahhh excellent, you're on the ball :)
> 
> yup, only missing unit tests and formal proofs.

ok you should be able to just import the class in test_div_sim.py and use it in
fu/div/test/test_pipe_caller.py

can i leave that with you as it's 11pm here?

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