[Libre-soc-bugs] [Bug 393] Hook up L2 Cache to Wishbone/LDST Wrappers

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jun 19 22:58:19 BST 2020


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
                 CC|                            |lkcl at lkcl.net

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
increnental strategy described here:

the idea is to first morph L0CacheBuffer to use the minerva LoadStoreInterface.

this to be done by creating a TestMemoryLoadStoreUnit (with associated unit
tests) that ignores the wishbone sbus entirely.

once L0CacheBuffer "talks" minerva LoadStoreInterface, it is plain sailing from
that point.

the only changes to the minerva loadstore.py at that point would be to widen
the buses to 64 bit.

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