# [Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jul 30 16:51:12 BST 2020

```https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #46 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #45)
> http://www.aholme.co.uk/6502/Main.htm
>
> apparently there is an algorithm called "SubGemini" which solves the
> recursive netlist walking issue: finding sub-circuit instances in a
> larger circuit.
>
> 1. Miles Ohlrich, Carl Ebeling, Eka Ginting and Lisa Sather. "SubGemini:
> Identifying Subcircuits Using a Fast Subgraph Isomorphism Algorithm," In
> Proceedings of the 30th IEEE/ACM Design Automation Conference, June 1993.

I will look into it if needs be. Thanks for the tips.

I'm almost done for the P&R of the sub-blocks of test_issuer, and now
it would be very helpful if you could provide me with a rough floorplan
of the blocks:

* fus (maybe an ordering of the FUs, but not mandatory).
* int
* fast
* pdecode2
* l0

Other blocks at core level, like the priority pickers are too small
to be taken into account as "blocks to place separately".

And maybe some hint about the big busses...

I'm finishing this because I'm stubborn, but it is already clear at 99%
that it will gives results *much* worse than the "flat" approach:

As we place each block indepandantly, we create huge contention points
at the border of most blocks due to the amount of large buses. Then we
have to route those buses *between* the blocks, forcing us to push
them farther apart, not even talking about the capacitance/drive problem.
Moreover, the box a block can stray too far from a square factor if we
want the placer to work (that is an AR between 0.5 and 2.0). There are
exceptions, but that's the general idea. It would be a problem for the
clock tree as it's depth may vary between blocks of different sizes.
And lastly, to reduce the size of the channels, we would need a careful
analysis of where to place the buses (and "combing" the bits to avoid
to "flip" a whole bus), which is a lengthy task.
So, if we compare a "flat" block with maybe up to 20% of margin space
and the sum of blocks at 5% to 20% of free space plus channels, the
winner is clear. Staf wins again.
The "good" block level is the core, I think.

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