[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jul 28 18:10:29 BST 2020


--- Comment #9 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)

> this again is the virtualisation of interrupts, not the actual interrupts. 
> cinsequently whilst the same registers appear (CPRR, PIPR) there's nothing
> about those.
> my feeling is that the spec has never been released: the qemu XICS code for
> example is written *by* someone at IBM who had internal access to it.

Oy gevalt! Such a headache, although I think Jacob may have found what we are
looking for:... will edit with reference to mailing list archives once they are
up-to-date enough to include jacob's mail.

from: Jacob Lifshay <programmerjake at gmail.com>
to: Libre-RISCV General Development <libre-riscv-dev at lists.libre-riscv.org>
date: Jul 28, 2020, 9:51 AM PDT
subject: Re: [libre-riscv-dev] how do we test external interrupts?

I found what looks like the reference source:
> This device emulates the XICS (eXternal Interrupt Controller
Specification) defined in PAPR.




I think this is the key part:

PowerPC External Interrupt Architecture:
<chapter  xmlns="http://docbook.org/ns/docbook"
  <title>Interrupt Controller</title>

  <para>This chapter specifies the requirements for the LoPAR interrupt
  controller. Platforms may chose to virtualize the interrupt controller or to
  provide the PowerPC External Interrupt option. </para>

    <title>Interrupt Controller Virtualization</title>
    <para>Virtualization of the interrupt controller is done through the
    Interrupt Support hcalls. See <xref

  <section xml:id="dbdoclet.50569331_29157">
    <title>PowerPC External Interrupt Option</title>
    <para>The PowerPC External Interrupt option is based upon a subset of the
    PowerPC External Interrupt Architecture. The PowerPC External Interrupt
    Architecture contains a register-level architectural definition of an
    control structure. This architecture defines means for assigning properties
    such as priority, destination, etc., to I/O and interprocessor interrupts,
    well as an interface for presenting them to processors. It supports both
    specific and distributed methods for interrupt delivery. See also
    <!-- FIXME: xref linkend="error_section"/--><citetitle>A PowerPC External
    <para>In NUMA platform configurations, the interrupt controllers may be
    configured in disjoint domains. The firmware makes the server numbers
    to any single OS image appear to come from a single space without
    This may be done by appropriately initializing the interrupt presentation
    controllers or the firmware may translate the server numbers presented to
it in
    RTAS calls before entering them into the interrupt controller registers.
The OS
    is made aware that certain interrupts are only served by certain servers by
    inclusion of the <emphasis
    property in the interrupt controller nodes.</para>

    <section xml:id="sec_ext_int_opt_req">
      <title>PowerPC External Interrupt Option Requirements</title>
      <para>The following are the requirements for the PowerPC External
      Interrupt option. Additional requirements and information relative to the
      option, when implemented with this option, are listed in <xref

I'll upload just this 'chapter' (only 750 lines of text) to the wiki?

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