[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jul 24 10:25:26 BST 2020


--- Comment #126 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i will commit this shortly.  do you note two things:

1) comments are added which "explain why".  removing comments is detrimental
   to communication and code maintenance.

2) is it now clear what i said: that the python slice numbering has to
   be LHS < RHS?  in each and every case (including TEs and TEe but
   now where field_slice is used 30, 31 you've *introduced* a bug)
   the BE indexing "LHS small number, RHS large number" is ***INVERTED***
   by the subtraction from 63.

with that commit (which i will do in a minute) you should now find bugs
and python exceptions come up when running the proof and the trap unit test
test_pipe_caller.py, which i will leave for you to fix.

diff --git a/src/soc/consts.py b/src/soc/consts.py
index fe29743e..8ed63eab 100644
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -13,12 +13,15 @@ def field_slice(start, end):
     where the start and end bits use IBM conventions.  start < end.
     The range specified is inclusive on both ends.
+    start = 63 - start
+    end = 63 - end
+    # XXX must do the endian-reversing BEFORE doing the comparison
+    # if done after, that instead asserts that (after modification)
+    # start *MUST* be greater than end!
     if start >= end:
         raise ValueError(
             "start ({}) must be less than end ({})".format(start, end)
-    start = 63 - start
-    end = 63 - end
     return slice(end, start + 1)

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