[Libre-soc-bugs] [Bug 439] New: generated op_divde appears to be incorrect

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=439

            Bug ID: 439
           Summary: generated op_divde appears to be incorrect
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: major
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
            Blocks: 324
   NLnet milestone: ---

got a backtrace:

Traceback (most recent call last):
  File "src/soc/fu/div/test/test_pipe_caller.py", line 359, in process
    yield from isa_sim.call(opname)
  File "/home/jacob/projects/libreriscv/soc/src/soc/decoder/isa/caller.py",
line 663, in call
    results = info.func(self, *inputs)
  File "/home/jacob/projects/libreriscv/soc/src/soc/decoder/isa/caller.py",
line 761, in decorator
    result = func(*args, **kwargs)
  File "/home/jacob/projects/libreriscv/soc/src/soc/decoder/isa/fixedarith.py",
line 893, in op_divde
    divisor[0:128] = concat([0 * 64], RB)
  File "/home/jacob/projects/libreriscv/soc/src/soc/decoder/selectable_int.py",
line 441, in selectconcat
    res.bits += i.bits
AttributeError: 'list' object has no attribute 'bits'

I'm on soc commit 8bf37997d31250126a664aeb3bd67ac0cd72a70c

generated code:
    @inject()
    def op_divde(self, RA, RB, RT):
        dividend = concat(0, repeat=128)
        dividend[0:128] = concat(RA, concat(0, repeat=64))
        divisor = concat(0, repeat=128)
        divisor[0:128] = concat([0 * 64], RB)
        if eq(divisor, concat(0, repeat=128)):
            overflow = 1
        else:
            result = DIVS(dividend, divisor)
            if eq(result[64:128], SelectableInt(value=0x0, bits=64)):
                RT = result[63:128]
                overflow = 0
            else:
                overflow = 1
        if eq(overflow, 1):
            RT[0:64] = undefined[0:64]
        return (overflow, RT,)


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=324
[Bug 324] create POWER DIV pipeline
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