[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #117 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 8fef04dc4954c146277e1534c89d013d7a4174d7 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Jul 22 20:08:29 2020 +0100

    sigh, auto-create some little/big-endian classes for accessing MSR/PI
fields

ok!  been meaning to do this for a while.

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