[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #107 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
due to PowerISA numbering, this *might be largernumber:smallernumber
and i do not know if that works as intended.

                comb += expected_msr[MSR.TEs:MSR.TEe+1].eq(0)


>>> l = [1,2,3,4]
>>> l[2:0]
[]

it doesn't.  it returns an empty list.

MSR.TEs i believe is *greater* than TSR.TEe.

    TEs = (63 - 53)    # Trace Enable (subfield)
    TEe = (63 - 54)    # Trace Enable (subfield)

>>> 63-53
10
>>> 63-54
9

it is.  so that means that the above is:

            expected_msr[10:9+1]

which is going to be an empty list.

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