[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jul 21 11:16:35 BST 2020


--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

damn.  completely missed this.  that when SRR1 is written to, bits
in MSR are also changed.  i cut/paste the microwatt code so as to
action it, but missed it


ok give me a mo to update that.

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