[Libre-soc-bugs] [Bug 421] TRAP pipeline formal correctness proof needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jul 21 00:00:45 BST 2020


--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Samuel A. Falvo II from comment #13)
> I should be more precise; I can find the instruction pseudo-code for TWI,
> et. al. easily enough.  What's missing is when the pseudocode says "TRAP"
> and dead-ends there.

ah, yes. i found that particularly obtuse.
i had to ask / work it out.

see trap function in ISACaller and in trap main_stage.py

CIA is stored in SRR0
NIA is set to 0x700
MSR is stored in SRR1
MSR is set to something.

>  What does that mean, precisely?  Even the chapter on
> Interrupts says that the behavior of traps is dependent on what causes the
> trap,

sigh yes there is a boatload of different behaviours, a whole ton of flags, you
will see a reference to where they start.

the 0x700 trap has its own definitions and meaning of the bits

0xc00 exception has different meanings.

it does all make sense once you know the context.

> and unless I missed something, nothing in that chapter mentions any of
> the trap instructions outside of system call.

to be honest i have no idea what tdi, twi etc are used for.

and again to be honest i am not going to worry about it.  all that matters is
getting the functionality right.

i agree it would be nice to know how rhey are used but i learned from my
reverse enhineering days very quickly that understanding or lack of is *not*
necessarily an impediment to forward progress.  it is a false correlation to
believe so.

>  I cannot find the place in
> the specs where fixed-point facility traps are discussed (even if only by
> reference).

this might be a good question to ask on openhdl-cores openpower foundation

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