[Libre-soc-bugs] [Bug 412] set up litex for peripherals and linking to core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Jul 18 15:30:59 BST 2020


--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hi florent, thank you for offering to help with this.


* we have a POWER9 compliant core written in nmigen
* therefore we need a hybrid combination of how both microwatt
  and Minerva are set up
* the do_finalize from "litex/soc/cores/cpu/minerva/core.py"
* the reset_address gcc_flags and setup from
* the wishbone buses are *64* bit data
* we use the *Minerva* Load/Store and Fetch code therefore the
  ibus and dbus can be set up according to how *Minerva* does it,
  *not* the "stall" method from microwatt.
* we actually support big *and* little-endian however please assume
  little for now.
* we do not unfortunately have a Debug bus (examining microwatt core.py)
* nor interrupts (yet)

now, i did notice that there is a general practice of creating a
repository that takes a *copy* of the core, in a repository named

the libre-soc codebase is so large (45,000 for the IEEE754 FP unit,
20,000 for the main core, 5,000 for the support library, nmutil)
that it would not only be impractical, it would be detrimental to
development to follow this pattern.

if it is absolutely necessary to have this subdirectory (named
pythondata-cpu-libre-soc) then what i would advocate is that we
add such a subdirectory *DIRECTLY* to the libre-soc main git
repository, populate it with the necessary files, and for development
purposes create a symbolic link in the litex directory to the
libre-soc directory, pythondata-cpu-libre-soc.

i am happy to give you commit access to the relevant libre-soc git
repositories, if you send me an id_rsa.pub.

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