[Libre-soc-bugs] [Bug 425] DIV overflow not being calculated correctly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=425

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ahh i think i now know why gtkwave (nmigen) "appeared" not to be working
and also why the overflow calculation wasn't working: you'd missed out
propagating the full set of parameters down the pipeline chain

class CoreBaseData(DIVInputData):
    def __init__(self, pspec, core_data_class):
        super().__init__(pspec)
        self.core = core_data_class(pspec.core_config)
        self.divisor_neg = Signal(reset_less=True)
        self.dividend_neg = Signal(reset_less=True)
        self.div_by_zero = Signal(reset_less=True)  <- missing
        self.dive_abs_ov32 = Signal(reset_less=True) <- missing
        self.dive_abs_ov64 = Signal(reset_less=True) <- missing


+++ b/src/soc/fu/div/core_stages.py
@@ -27,10 +27,12 @@ class DivCoreBaseStage(PipeModBase):
     def elaborate(self, platform):
         m = Module()

+        # pass-through on non-core parameters
         m.d.comb += self.o.eq_without_core(self.i)

         m.submodules.core = self.core

+        # copy parameters to/from divremsqrt core into the Base, here.
         m.d.comb += self.core.i.eq(self.i.core)
         m.d.comb += self.o.core.eq(self.core.o)

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index fa67aded..02f169f9 100644
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -67,7 +67,10 @@ class CoreBaseData(DIVInputData):
     def eq_without_core(self, rhs):
         return super().eq(rhs) + \
             [self.divisor_neg.eq(rhs.divisor_neg),
-             self.dividend_neg.eq(rhs.dividend_neg)]
+             self.dividend_neg.eq(rhs.dividend_neg),
+             self.dive_abs_ov32.eq(rhs.dive_abs_ov32),
+             self.dive_abs_ov64.eq(rhs.dive_abs_ov64),
+             self.div_by_zero.eq(rhs.div_by_zero)]

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